[Libva] [PATCH 09/12] ROI:enable on gen8 and gen9
Pengfei Qu
Pengfei.Qu at intel.com
Tue Jul 19 04:50:58 UTC 2016
v1:
ROI enable on gen8 and gen9
Enable GPU to construct GPU command under ROI scenario
fix roi attrib config incorrectly
Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
Signed-off-by: Pengfei Qu <Pengfei.Qu at intel.com>
---
src/gen6_mfc_common.c | 62 ++++++++++++++++++++++++++++++---------------------
src/gen8_mfc.c | 55 ++++++++++++++++++++++++++++++++-------------
src/gen8_vme.c | 21 ++++++++++++++++-
src/gen9_mfc.c | 35 ++++++++++++++---------------
src/gen9_vme.c | 40 ++++++++++++++++++++++++++++-----
src/i965_drv_video.c | 15 ++++++++-----
6 files changed, 156 insertions(+), 72 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index 876ba41..cec5f1a 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1821,7 +1821,7 @@ intel_h264_enc_roi_cbr(VADriverContextP ctx,
bool quickfill = 0;
ROIRegionParam param_regions[I965_MAX_NUM_ROI_REGIONS];
- int num_roi;
+ int num_roi = 0;
int i,j;
float temp;
@@ -1837,10 +1837,21 @@ intel_h264_enc_roi_cbr(VADriverContextP ctx,
struct gen6_vme_context *vme_context = encoder_context->vme_context;
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
- max_delta = pMiscParamROI->max_delta_qp;
- min_delta = pMiscParamROI->min_delta_qp;
-
- num_roi = (pMiscParamROI->num_roi > I965_MAX_NUM_ROI_REGIONS) ? I965_MAX_NUM_ROI_REGIONS : pMiscParamROI->num_roi;
+ if(pMiscParamROI != NULL)
+ {
+ max_delta = pMiscParamROI->max_delta_qp;
+ min_delta = pMiscParamROI->min_delta_qp;
+
+ num_roi = (pMiscParamROI->num_roi > I965_MAX_NUM_ROI_REGIONS) ? I965_MAX_NUM_ROI_REGIONS : pMiscParamROI->num_roi;
+
+ /* currently roi_value_is_qp_delta is the only supported mode of priority.
+ *
+ * qp_delta set by user is added to base_qp, which is then clapped by
+ * [base_qp-min_delta, base_qp+max_delta].
+ */
+ pMiscParamROI->roi_flags.bits.roi_value_is_qp_delta = 1;
+ assert (pMiscParamROI->roi_flags.bits.roi_value_is_qp_delta);
+ }
/* when the base_qp is lower than 12, the quality is quite good based
* on the H264 test experience.
@@ -1852,13 +1863,6 @@ intel_h264_enc_roi_cbr(VADriverContextP ctx,
goto qp_fill;
}
- /* currently roi_value_is_qp_delta is the only supported mode of priority.
- *
- * qp_delta set by user is added to base_qp, which is then clapped by
- * [base_qp-min_delta, base_qp+max_delta].
- */
- assert (pMiscParamROI->roi_flags.bits.roi_value_is_qp_delta);
-
sum_roi = 0.0f;
roi_area = 0;
for (i = 0; i < num_roi; i++) {
@@ -1937,8 +1941,9 @@ intel_h264_enc_roi_config(VADriverContextP ctx,
{
char *qp_ptr;
int i, j;
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
VAEncMiscParameterBuffer* pMiscParamROI;
- VAEncMiscParameterBufferROI *pParamROI;
+ VAEncMiscParameterBufferROI *pParamROI = NULL;
VAEncROI *region_roi;
struct gen6_vme_context *vme_context = encoder_context->vme_context;
struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
@@ -1946,26 +1951,27 @@ intel_h264_enc_roi_config(VADriverContextP ctx,
int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
- int row_start, row_end, col_start, col_end;
- int num_roi;
+ int row_start, row_end, col_start, col_end;
+ int num_roi;
vme_context->roi_enabled = 0;
encoder_context->soft_batch_force = 0;
- /* Restriction: Disable ROI when multi-slice is enabled */
+
+ /* Restriction: Disable ROI when multi-slice is enabled */
if (!encoder_context->context_roi || (encode_state->num_slice_params_ext > 1))
return;
- if (encode_state->misc_param[VAEncMiscParameterTypeROI] == NULL) {
- return;
- }
+ if (encode_state->misc_param[VAEncMiscParameterTypeROI] != NULL) {
+ pMiscParamROI = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeROI]->buffer;
+ pParamROI = (VAEncMiscParameterBufferROI *)pMiscParamROI->data;
- pMiscParamROI = (VAEncMiscParameterBuffer*)encode_state->misc_param[VAEncMiscParameterTypeROI]->buffer;
- pParamROI = (VAEncMiscParameterBufferROI *)pMiscParamROI->data;
+ /* check whether number of ROI is correct */
+ num_roi = (pParamROI->num_roi > I965_MAX_NUM_ROI_REGIONS) ? I965_MAX_NUM_ROI_REGIONS : pParamROI->num_roi;
- /* check whether number of ROI is correct */
- num_roi = (pParamROI->num_roi > I965_MAX_NUM_ROI_REGIONS) ? I965_MAX_NUM_ROI_REGIONS : pParamROI->num_roi;
+ if(num_roi > 0)
+ vme_context->roi_enabled = 1;
+ }
- vme_context->roi_enabled = 1;
if ((vme_context->saved_width_mbs != width_in_mbs) ||
(vme_context->saved_height_mbs != height_in_mbs)) {
@@ -2031,9 +2037,13 @@ intel_h264_enc_roi_config(VADriverContextP ctx,
*/
vme_context->roi_enabled = 0;
}
- if (vme_context->roi_enabled)
+ if (vme_context->roi_enabled)
encoder_context->soft_batch_force = 1;
- return;
+
+ if( IS_GEN8(i965->intel.device_info) || IS_GEN9(i965->intel.device_info) )
+ encoder_context->soft_batch_force = 0;
+
+ return;
}
/* HEVC */
diff --git a/src/gen8_mfc.c b/src/gen8_mfc.c
index 1f8e57b..186bb9b 100644
--- a/src/gen8_mfc.c
+++ b/src/gen8_mfc.c
@@ -939,8 +939,6 @@ gen8_mfc_avc_slice_state(VADriverContextP ctx,
#define AVC_INTER_MV_OFFSET 48
#define AVC_RDO_MASK 0xFFFF
-#if MFC_SOFTWARE_BATCH
-
static int
gen8_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
int qp,unsigned int *msg,
@@ -1114,6 +1112,7 @@ gen8_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
int is_intra = slice_type == SLICE_TYPE_I;
int qp_slice;
+ int qp_mb;
qp_slice = qp;
if (rate_control_mode == VA_RC_CBR) {
@@ -1156,20 +1155,24 @@ gen8_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
x = i % width_in_mbs;
y = i / width_in_mbs;
msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block);
+ if (vme_context->roi_enabled) {
+ qp_mb = *(vme_context->qp_per_mb + i);
+ } else
+ qp_mb = qp;
if (is_intra) {
assert(msg);
- gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
+ gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
} else {
int inter_rdo, intra_rdo;
inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK;
intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK;
offset = i * vme_context->vme_output.size_block + AVC_INTER_MV_OFFSET;
if (intra_rdo < inter_rdo) {
- gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
+ gen8_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
} else {
msg += AVC_INTER_MSG_OFFSET;
- gen8_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
+ gen8_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp_mb, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
}
}
}
@@ -1217,7 +1220,6 @@ gen8_mfc_avc_software_batchbuffer(VADriverContextP ctx,
return batch_bo;
}
-#else
static void
gen8_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
@@ -1374,6 +1376,8 @@ gen8_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
int last_mb, slice_end_x, slice_end_y;
int remaining_mb = total_mbs;
uint32_t fwd_ref , bwd_ref, mb_flag;
+ char tmp_qp;
+ int number_roi_mbs, max_mb_cmds, i;
last_mb = slice_param->macroblock_address + total_mbs - 1;
slice_end_x = last_mb % width_in_mbs;
@@ -1401,13 +1405,32 @@ gen8_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
number_mb_cmds = width_in_mbs;
}
+ max_mb_cmds = number_mb_cmds;
+
do {
- if (number_mb_cmds >= remaining_mb) {
- number_mb_cmds = remaining_mb;
- }
mb_x = (slice_param->macroblock_address + starting_offset) % width_in_mbs;
mb_y = (slice_param->macroblock_address + starting_offset) / width_in_mbs;
+ number_mb_cmds = max_mb_cmds;
+ if (vme_context->roi_enabled) {
+
+ number_roi_mbs = 1;
+ tmp_qp = *(vme_context->qp_per_mb + starting_offset);
+ for (i = 1; i < max_mb_cmds; i++) {
+ if (tmp_qp != *(vme_context->qp_per_mb + starting_offset + i))
+ break;
+
+ number_roi_mbs++;
+ }
+
+ number_mb_cmds = number_roi_mbs;
+ qp = tmp_qp;
+ }
+
+ if (number_mb_cmds >= remaining_mb) {
+ number_mb_cmds = remaining_mb;
+ }
+
gen8_mfc_batchbuffer_emit_object_command(batch,
mb_flag,
head_offset,
@@ -1585,8 +1608,6 @@ gen8_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
return mfc_context->aux_batchbuffer_surface.bo;
}
-#endif
-
static void
gen8_mfc_avc_pipeline_programing(VADriverContextP ctx,
struct encode_state *encode_state,
@@ -1601,11 +1622,11 @@ gen8_mfc_avc_pipeline_programing(VADriverContextP ctx,
return;
}
-#if MFC_SOFTWARE_BATCH
- slice_batch_bo = gen8_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
-#else
- slice_batch_bo = gen8_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
-#endif
+ if (encoder_context->soft_batch_force)
+ slice_batch_bo = gen8_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
+ else
+ slice_batch_bo = gen8_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
+
// begin programing
intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
@@ -1639,6 +1660,8 @@ gen8_mfc_avc_encode_picture(VADriverContextP ctx,
unsigned int rate_control_mode = encoder_context->rate_control_mode;
int current_frame_bits_size;
int sts;
+
+ encoder_context->soft_batch_force = 0;
for (;;) {
gen8_mfc_init(ctx, encode_state, encoder_context);
diff --git a/src/gen8_vme.c b/src/gen8_vme.c
index 4f6ce06..0fcc585 100644
--- a/src/gen8_vme.c
+++ b/src/gen8_vme.c
@@ -562,6 +562,17 @@ gen8_vme_fill_vme_batchbuffer(VADriverContextP ctx,
int mb_x = 0, mb_y = 0;
int i, s;
unsigned int *command_ptr;
+ struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
+ int qp;
+ int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+ int qp_mb, qp_index;
+
+ if (encoder_context->rate_control_mode == VA_RC_CQP)
+ qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ else
+ qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
command_ptr = vme_context->vme_batchbuffer.bo->virtual;
@@ -599,7 +610,7 @@ gen8_vme_fill_vme_batchbuffer(VADriverContextP ctx,
if ((i == mb_width) && slice_mb_x) {
mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
}
- *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
+ *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
*command_ptr++ = kernel;
*command_ptr++ = 0;
*command_ptr++ = 0;
@@ -609,6 +620,13 @@ gen8_vme_fill_vme_batchbuffer(VADriverContextP ctx,
/*inline data */
*command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
*command_ptr++ = ((encoder_context->quality_level << 24) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
+ /* qp occupies one byte */
+ if (vme_context->roi_enabled) {
+ qp_index = mb_y * mb_width + mb_x;
+ qp_mb = *(vme_context->qp_per_mb + qp_index);
+ } else
+ qp_mb = qp;
+ *command_ptr++ = qp_mb;
*command_ptr++ = CMD_MEDIA_STATE_FLUSH;
*command_ptr++ = 0;
@@ -725,6 +743,7 @@ static VAStatus gen8_vme_prepare(VADriverContextP ctx,
intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
intel_h264_initialize_mbmv_cost(ctx, encode_state, encoder_context);
+ intel_h264_enc_roi_config(ctx, encode_state, encoder_context);
/*Setup all the memory object*/
gen8_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
diff --git a/src/gen9_mfc.c b/src/gen9_mfc.c
index 6cca579..109e697 100644
--- a/src/gen9_mfc.c
+++ b/src/gen9_mfc.c
@@ -47,8 +47,6 @@
#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index)
#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
-#define MFC_SOFTWARE_HASWELL 1
-
#define B0_STEP_REV 2
#define IS_STEPPING_BPLUS(i965) ((i965->intel.revision) >= B0_STEP_REV)
@@ -856,8 +854,6 @@ gen9_mfc_avc_slice_state(VADriverContextP ctx,
}
-#ifdef MFC_SOFTWARE_HASWELL
-
static int
gen9_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb,
int qp,unsigned int *msg,
@@ -1037,6 +1033,7 @@ gen9_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
int is_intra = slice_type == SLICE_TYPE_I;
int qp_slice;
+ int qp_mb;
qp_slice = qp;
if (rate_control_mode == VA_RC_CBR) {
@@ -1080,19 +1077,24 @@ gen9_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
y = i / width_in_mbs;
msg = (unsigned int *) (msg_ptr + i * vme_context->vme_output.size_block);
+ if (vme_context->roi_enabled) {
+ qp_mb = *(vme_context->qp_per_mb + i);
+ } else
+ qp_mb = qp;
+
if (is_intra) {
assert(msg);
- gen9_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
+ gen9_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
} else {
int inter_rdo, intra_rdo;
inter_rdo = msg[AVC_INTER_RDO_OFFSET] & AVC_RDO_MASK;
intra_rdo = msg[AVC_INTRA_RDO_OFFSET] & AVC_RDO_MASK;
offset = i * vme_context->vme_output.size_block + AVC_INTER_MV_OFFSET;
if (intra_rdo < inter_rdo) {
- gen9_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
+ gen9_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp_mb, msg, encoder_context, 0, 0, slice_batch);
} else {
msg += AVC_INTER_MSG_OFFSET;
- gen9_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
+ gen9_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp_mb, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
}
}
}
@@ -1142,8 +1144,6 @@ gen9_mfc_avc_software_batchbuffer(VADriverContextP ctx,
return batch_bo;
}
-#else
-
static void
gen9_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
struct encode_state *encode_state,
@@ -1537,7 +1537,6 @@ gen9_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
return mfc_context->mfc_batchbuffer_surface.bo;
}
-#endif
static void
gen9_mfc_avc_pipeline_programing(VADriverContextP ctx,
@@ -1553,11 +1552,11 @@ gen9_mfc_avc_pipeline_programing(VADriverContextP ctx,
return;
}
-#ifdef MFC_SOFTWARE_HASWELL
- slice_batch_bo = gen9_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
-#else
- slice_batch_bo = gen9_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
-#endif
+ if (encoder_context->soft_batch_force)
+ slice_batch_bo = gen9_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
+ else
+ slice_batch_bo = gen9_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
+
// begin programing
intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
@@ -1705,12 +1704,12 @@ Bool gen9_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *e
{
struct gen6_mfc_context *mfc_context = NULL;
-#if MFC_SOFTWARE_HASWELL
+
if ((encoder_context->codec == CODEC_H264) ||
(encoder_context->codec == CODEC_H264_MVC)) {
- return gen8_mfc_context_init(ctx, encoder_context);
+ return gen8_mfc_context_init(ctx, encoder_context);
}
-#endif
+
if ((encoder_context->codec == CODEC_VP8) ||
(encoder_context->codec == CODEC_MPEG2))
diff --git a/src/gen9_vme.c b/src/gen9_vme.c
index 5f9b796..a2c65b3 100644
--- a/src/gen9_vme.c
+++ b/src/gen9_vme.c
@@ -352,6 +352,9 @@ gen9_vme_surface_setup(VADriverContextP ctx,
/* VME output */
gen9_vme_avc_output_buffer_setup(ctx, encode_state, 3, encoder_context);
gen9_vme_avc_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
+ intel_h264_setup_cost_surface(ctx, encode_state, encoder_context,
+ BINDING_TABLE_OFFSET(INTEL_COST_TABLE_OFFSET),
+ SURFACE_STATE_OFFSET(INTEL_COST_TABLE_OFFSET));
return VA_STATUS_SUCCESS;
}
@@ -603,6 +606,17 @@ gen9_vme_fill_vme_batchbuffer(VADriverContextP ctx,
int mb_x = 0, mb_y = 0;
int i, s;
unsigned int *command_ptr;
+ struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
+ VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
+ VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
+ int qp;
+ int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
+ int qp_mb, qp_index;
+
+ if (encoder_context->rate_control_mode == VA_RC_CQP)
+ qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+ else
+ qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
command_ptr = vme_context->vme_batchbuffer.bo->virtual;
@@ -640,7 +654,7 @@ gen9_vme_fill_vme_batchbuffer(VADriverContextP ctx,
if ((i == mb_width) && slice_mb_x) {
mb_intra_ub &= ~(INTRA_PRED_AVAIL_FLAG_D);
}
- *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
+ *command_ptr++ = (CMD_MEDIA_OBJECT | (9 - 2));
*command_ptr++ = kernel;
*command_ptr++ = 0;
*command_ptr++ = 0;
@@ -650,6 +664,13 @@ gen9_vme_fill_vme_batchbuffer(VADriverContextP ctx,
/*inline data */
*command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
*command_ptr++ = ((encoder_context->quality_level << 24) | (1 << 16) | transform_8x8_mode_flag | (mb_intra_ub << 8));
+ /* qp occupies one byte */
+ if (vme_context->roi_enabled) {
+ qp_index = mb_y * mb_width + mb_x;
+ qp_mb = *(vme_context->qp_per_mb + qp_index);
+ } else
+ qp_mb = qp;
+ *command_ptr++ = qp_mb;
*command_ptr++ = CMD_MEDIA_STATE_FLUSH;
*command_ptr++ = 0;
@@ -767,6 +788,8 @@ static VAStatus gen9_vme_prepare(VADriverContextP ctx,
}
intel_vme_update_mbmv_cost(ctx, encode_state, encoder_context);
+ intel_h264_initialize_mbmv_cost(ctx, encode_state, encoder_context);
+ intel_h264_enc_roi_config(ctx, encode_state, encoder_context);
/*Setup all the memory object*/
gen9_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
@@ -1771,10 +1794,17 @@ gen9_vme_context_destroy(void *context)
dri_bo_unreference(vme_context->vme_batchbuffer.bo);
vme_context->vme_batchbuffer.bo = NULL;
- if (vme_context->vme_state_message) {
- free(vme_context->vme_state_message);
- vme_context->vme_state_message = NULL;
- }
+ free(vme_context->vme_state_message);
+ vme_context->vme_state_message = NULL;
+
+ dri_bo_unreference(vme_context->i_qp_cost_table);
+ vme_context->i_qp_cost_table = NULL;
+
+ dri_bo_unreference(vme_context->p_qp_cost_table);
+ vme_context->p_qp_cost_table = NULL;
+
+ dri_bo_unreference(vme_context->b_qp_cost_table);
+ vme_context->b_qp_cost_table = NULL;
free(vme_context);
}
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 9812dff..94f8d36 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1049,15 +1049,18 @@ i965_GetConfigAttributes(VADriverContextP ctx,
break;
case VAConfigAttribEncROI:
- if ((entrypoint == VAEntrypointEncSliceLP) &&
+ if ((entrypoint == VAEntrypointEncSlice ||
+ entrypoint == VAEntrypointEncSliceLP) &&
(profile == VAProfileH264ConstrainedBaseline ||
profile == VAProfileH264Main ||
profile == VAProfileH264High ) &&
- (IS_GEN7(i965->intel.device_info))) {
- VAConfigAttribValEncROI *roi_config = (VAConfigAttribValEncROI *)&(attrib_list[i].value);
- roi_config->bits.num_roi_regions = I965_MAX_NUM_ROI_REGIONS;
- roi_config->bits.roi_rc_priority_support = 0;
- roi_config->bits.roi_rc_qp_delat_support = 1;
+ (IS_GEN7(i965->intel.device_info)||
+ IS_GEN8(i965->intel.device_info)||
+ IS_GEN9(i965->intel.device_info))){
+ VAConfigAttribValEncROI *roi_config = (VAConfigAttribValEncROI *)&(attrib_list[i].value);
+ roi_config->bits.num_roi_regions = I965_MAX_NUM_ROI_REGIONS;
+ roi_config->bits.roi_rc_priority_support = 0;
+ roi_config->bits.roi_rc_qp_delat_support = 1;
}
break;
--
2.7.4
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