[Libva] [Libva-intel-driver][PATCH 05/10] Add some utility functions for MI commands for GEN9
Xiang, Haihao
haihao.xiang at intel.com
Wed May 4 02:59:00 UTC 2016
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
Reviewed-By: Sean V Kelley <sean.v.kelley at intel.com>
---
src/i965_gpe_utils.c | 147 +++++++++++++++++++++++++++++++++++++++++++++++++++
src/i965_gpe_utils.h | 102 +++++++++++++++++++++++++++++++++++
src/intel_driver.h | 19 +++++++
3 files changed, 268 insertions(+)
diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index fe000c1..bcf5dcf 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -1424,3 +1424,150 @@ i965_unmap_gpe_resource(struct i965_gpe_resource *res)
res->map = NULL;
}
+
+void
+gen9_gpe_mi_flush_dw(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_flush_dw_parameter *params)
+{
+ int video_pipeline_cache_invalidate = 0;
+ int post_sync_operation = MI_FLUSH_DW_NOWRITE;
+
+ if (params->video_pipeline_cache_invalidate)
+ video_pipeline_cache_invalidate = MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE;
+
+ if (params->bo)
+ post_sync_operation = MI_FLUSH_DW_WRITE_QWORD;
+
+ __OUT_BATCH(batch, (MI_FLUSH_DW2 |
+ video_pipeline_cache_invalidate |
+ post_sync_operation |
+ (5 - 2))); /* Always use PPGTT */
+
+ if (params->bo) {
+ __OUT_RELOC64(batch,
+ params->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ params->offset);
+ } else {
+ __OUT_BATCH(batch, 0);
+ __OUT_BATCH(batch, 0);
+ }
+
+ __OUT_BATCH(batch, params->dw0);
+ __OUT_BATCH(batch, params->dw1);
+}
+
+void
+gen9_gpe_mi_store_data_imm(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_store_data_imm_parameter *params)
+{
+ if (params->is_qword) {
+ __OUT_BATCH(batch, MI_STORE_DATA_IMM |
+ (1 << 21) |
+ (5 - 2)); /* Always use PPGTT */
+ } else {
+ __OUT_BATCH(batch, MI_STORE_DATA_IMM | (4 - 2)); /* Always use PPGTT */
+ }
+
+ __OUT_RELOC64(batch,
+ params->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ params->offset);
+ __OUT_BATCH(batch, params->dw0);
+
+ if (params->is_qword)
+ __OUT_BATCH(batch, params->dw1);
+}
+
+void
+gen9_gpe_mi_store_register_mem(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_store_register_mem_parameter *params)
+{
+ __OUT_BATCH(batch, (MI_STORE_REGISTER_MEM | (4 - 2))); /* Always use PPGTT */
+ __OUT_BATCH(batch, params->mmio_offset);
+ __OUT_RELOC64(batch,
+ params->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ params->offset);
+}
+
+void
+gen9_gpe_mi_load_register_mem(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_mem_parameter *params)
+{
+ __OUT_BATCH(batch, (MI_LOAD_REGISTER_MEM | (4 - 2))); /* Always use PPGTT */
+ __OUT_BATCH(batch, params->mmio_offset);
+ __OUT_RELOC64(batch,
+ params->bo,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+ params->offset);
+}
+
+void
+gen9_gpe_mi_load_register_imm(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_imm_parameter *params)
+{
+ __OUT_BATCH(batch, (MI_LOAD_REGISTER_IMM | (3 - 2)));
+ __OUT_BATCH(batch, params->mmio_offset);
+ __OUT_BATCH(batch, params->data);
+}
+
+void
+gen9_gpe_mi_load_register_reg(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_reg_parameter *params)
+{
+ __OUT_BATCH(batch, (MI_LOAD_REGISTER_REG | (3 - 2)));
+ __OUT_BATCH(batch, params->src_mmio_offset);
+ __OUT_BATCH(batch, params->dst_mmio_offset);
+}
+
+void
+gen9_gpe_mi_math(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_math_parameter *params)
+{
+ __OUT_BATCH(batch, (MI_MATH | (params->num_instructions - 1)));
+ intel_batchbuffer_data(batch, params->instruction_list, params->num_instructions * 4);
+}
+
+void
+gen9_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_conditional_batch_buffer_end_parameter *params)
+{
+ int compare_mask_mode_enabled = MI_COMPARE_MASK_MODE_ENANBLED;
+
+ if (params->compare_mask_mode_disabled)
+ compare_mask_mode_enabled = 0;
+
+ __OUT_BATCH(batch, (MI_CONDITIONAL_BATCH_BUFFER_END |
+ (1 << 21) |
+ compare_mask_mode_enabled |
+ (4 - 2))); /* Always use PPGTT */
+ __OUT_BATCH(batch, params->compare_data);
+ __OUT_RELOC64(batch,
+ params->bo,
+ I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
+ params->offset);
+}
+
+void
+gen9_gpe_mi_batch_buffer_start(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_batch_buffer_start_parameter *params)
+{
+ __OUT_BATCH(batch, (MI_BATCH_BUFFER_START |
+ (!!params->is_second_level << 22) |
+ (!params->use_global_gtt << 8) |
+ (1 << 0)));
+ __OUT_RELOC64(batch,
+ params->bo,
+ I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
+ params->offset);
+}
diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h
index e3dd82b..f3164b4 100644
--- a/src/i965_gpe_utils.h
+++ b/src/i965_gpe_utils.h
@@ -159,6 +159,72 @@ struct i965_gpe_context
int curbe_size;
};
+struct gpe_mi_flush_dw_parameter
+{
+ dri_bo *bo;
+ unsigned int offset;
+ unsigned int video_pipeline_cache_invalidate;
+ unsigned int dw0;
+ unsigned int dw1;
+};
+
+struct gpe_mi_store_data_imm_parameter
+{
+ dri_bo *bo;
+ unsigned int is_qword;
+ unsigned int offset;
+ unsigned int dw0;
+ unsigned int dw1;
+};
+
+struct gpe_mi_store_register_mem_parameter
+{
+ dri_bo *bo;
+ unsigned int offset;
+ unsigned int mmio_offset;
+};
+
+struct gpe_mi_load_register_mem_parameter
+{
+ dri_bo *bo;
+ unsigned int offset;
+ unsigned int mmio_offset;
+};
+
+struct gpe_mi_load_register_imm_parameter
+{
+ unsigned int data;
+ unsigned int mmio_offset;
+};
+
+struct gpe_mi_load_register_reg_parameter
+{
+ unsigned int src_mmio_offset;
+ unsigned int dst_mmio_offset;
+};
+
+struct gpe_mi_math_parameter
+{
+ unsigned int num_instructions;
+ unsigned int *instruction_list;
+};
+
+struct gpe_mi_conditional_batch_buffer_end_parameter
+{
+ dri_bo *bo;
+ unsigned int offset;
+ unsigned int compare_mask_mode_disabled;
+ unsigned int compare_data;
+};
+
+struct gpe_mi_batch_buffer_start_parameter
+{
+ dri_bo *bo;
+ unsigned int offset;
+ unsigned int is_second_level;
+ unsigned int use_global_gtt;
+};
+
void i965_gpe_context_destroy(struct i965_gpe_context *gpe_context);
void i965_gpe_context_init(VADriverContextP ctx,
struct i965_gpe_context *gpe_context);
@@ -272,4 +338,40 @@ void *i965_map_gpe_resource(struct i965_gpe_resource *res);
void i965_unmap_gpe_resource(struct i965_gpe_resource *res);
+void gen9_gpe_mi_flush_dw(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_flush_dw_parameter *params);
+
+void gen9_gpe_mi_store_data_imm(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_store_data_imm_parameter *params);
+
+void gen9_gpe_mi_store_register_mem(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_store_register_mem_parameter *params);
+
+void gen9_gpe_mi_load_register_mem(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_mem_parameter *params);
+
+void gen9_gpe_mi_load_register_imm(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_imm_parameter *params);
+
+void gen9_gpe_mi_load_register_reg(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_load_register_reg_parameter *params);
+
+void gen9_gpe_mi_math(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_math_parameter *params);
+
+void gen9_gpe_mi_conditional_batch_buffer_end(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_conditional_batch_buffer_end_parameter *params);
+
+void gen9_gpe_mi_batch_buffer_start(VADriverContextP ctx,
+ struct intel_batchbuffer *batch,
+ struct gpe_mi_batch_buffer_start_parameter *params);
+
#endif /* _I965_GPE_UTILS_H_ */
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 07a2274..f60374c 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -31,7 +31,26 @@
#define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
+#define MI_FLUSH_DW2 (CMD_MI | (0x26 << 23) | 0x3)
#define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
+#define MI_FLUSH_DW_NOWRITE (0 << 14)
+#define MI_FLUSH_DW_WRITE_QWORD (1 << 14)
+#define MI_FLUSH_DW_WRITE_TIME (3 << 14)
+
+#define MI_STORE_DATA_IMM (CMD_MI | (0x20 << 23))
+
+#define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23))
+
+#define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
+
+#define MI_LOAD_REGISTER_MEM (CMD_MI | (0x29 << 23))
+
+#define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
+
+#define MI_MATH (CMD_MI | (0x1A << 23))
+
+#define MI_CONDITIONAL_BATCH_BUFFER_END (CMD_MI | (0x36 << 23))
+#define MI_COMPARE_MASK_MODE_ENANBLED (1 << 19)
#define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
#define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
--
1.9.1
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