[Libva] [PATCH 2/8] Add the 10-bit flag for MEDIA_BLOCK_RW operation on 10bit surface

[Zhao Yakui]

Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
---
 src/i965_gpe_utils.c | 16 ++++++++++++----
 src/i965_gpe_utils.h |  1 +
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/i965_gpe_utils.c b/src/i965_gpe_utils.c
index a29237b..3cd41e8 100644
--- a/src/i965_gpe_utils.c
+++ b/src/i965_gpe_utils.c
@@ -1864,8 +1864,12 @@ gen9_gpe_context_add_surface(struct i965_gpe_context *gpe_context,
         height = gpe_resource->height / 2;
         pitch = gpe_resource->pitch;
 
-        if (gpe_surface->is_media_block_rw)
-            width = (ALIGN(width, 4) >> 2);
+        if (gpe_surface->is_media_block_rw) {
+            if (gpe_surface->is_10bit)
+                width = (ALIGN(width * 2, 4) >> 2);
+            else
+                width = (ALIGN(width, 4) >> 2);
+        }
 
         if (tiling == I915_TILING_Y) {
             tile_alignment = 32;
@@ -1897,8 +1901,12 @@ gen9_gpe_context_add_surface(struct i965_gpe_context *gpe_context,
         height = gpe_resource->height;
         pitch = gpe_resource->pitch;
 
-        if (gpe_surface->is_media_block_rw)
-            width = (ALIGN(width, 4) >> 2);
+        if (gpe_surface->is_media_block_rw) {
+            if (gpe_surface->is_10bit)
+                width = (ALIGN(width * 2, 4) >> 2);
+            else
+                width = (ALIGN(width, 4) >> 2);
+        }
 
         gen9_gpe_set_2d_surface_state(ss,
                                       gpe_surface->cacheability_control,
diff --git a/src/i965_gpe_utils.h b/src/i965_gpe_utils.h
index 39a6fad..c56d3d5 100644
--- a/src/i965_gpe_utils.h
+++ b/src/i965_gpe_utils.h
@@ -417,6 +417,7 @@ struct i965_gpe_surface
     unsigned int is_uv_surface:1;
     unsigned int is_media_block_rw:1;
     unsigned int is_raw_buffer:1;
+    unsigned int is_10bit     :1;
 
     unsigned int vert_line_stride_offset;
     unsigned int vert_line_stride;
-- 
2.8.3