[Libva] [PATCH 8/8] Align coordinate/width of DST rect for 10-bit VPP conversion

[Xiang, Haihao]

LGTM.

> This is the HW requirement and it is handled internally.
> 
> Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
> ---
>  src/gen75_picture_process.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/src/gen75_picture_process.c
> b/src/gen75_picture_process.c
> index 4f7f794..3c2e251 100644
> --- a/src/gen75_picture_process.c
> +++ b/src/gen75_picture_process.c
> @@ -213,6 +213,8 @@ gen75_proc_picture(VADriverContextP ctx,
>              intel_gpe_support_10bit_scaling(proc_ctx)) {
>              struct i965_proc_context *gpe_proc_ctx;
>              struct i965_surface src_surface, dst_surface;
> +            unsigned int tmp_width, tmp_x;
> +
>  
>              src_surface.base = (struct object_base *)obj_src_surf;
>              src_surface.type = I965_SURFACE_TYPE_SURFACE;
> @@ -220,6 +222,12 @@ gen75_proc_picture(VADriverContextP ctx,
>              dst_surface.type = I965_SURFACE_TYPE_SURFACE;
>              gpe_proc_ctx = (struct i965_proc_context *)proc_ctx-
> >vpp_fmt_cvt_ctx;
>  
> +            tmp_x = ALIGN_FLOOR(dst_rect.x, 2);
> +            tmp_width = dst_rect.x + dst_rect.width;
> +            tmp_width = tmp_width - tmp_x;
> +            dst_rect.x = tmp_x;
> +            dst_rect.width = tmp_width;
> +
>              return gen9_p010_scaling_post_processing(ctx,
> &gpe_proc_ctx->pp_context,
>                                                       &src_surface,
> &src_rect,
>                                                       &dst_surface,
> &dst_rect);