[Mesa-announce] [ANNOUNCE] mesa 17.0.0-rc2

Emil Velikov emil.l.velikov at gmail.com
Wed Jan 25 13:33:33 UTC 2017

The second release candidate for Mesa 17.0.0 is now available.

Andres Rodriguez (2):
      vulkan/wsi: clarify the severity of lack of DRI3 v2
      radv: fix include order for installed headers v2

Bruce Cherniak (1):
      swr: Prune empty nodes in CalculateProcessorTopology.

Dave Airlie (1):
      gallivm: use #ifdef not #if for PIPE_ARCH_BIG_ENDIAN

Emil Velikov (1):
      Update version to 17.0.0-rc2

George Kyriazis (1):
      swr: Align query results allocation

Grazvydas Ignotas (1):
      radv: don't resubmit the same cs over and over while tracing

Jason Ekstrand (2):
      intel/blorp/copy: Properly handle clear colors for CCS_E images
      nir/search: Use the correct bit size for integer comparisons

Lionel Landwerlin (2):
      spirv: don't assert with location decorations on non i/o variables
      anv: don't require render target isl bit for depth/stencil surfaces

Marek Olšák (2):
      radeonsi: don't forget to add HTILE to the buffer list for texturing
      radeonsi: always set the TCL1_ACTION_ENA when invalidating L2

Nicolai Hähnle (7):
      mesa/main: fix meta caller of _mesa_ClampColor
      radeonsi: fix texture gather on stencil textures
      r600: double multiply can handle only one multiply at a time
      r600: factor out cayman_emit_unary_double_raw
      r600: implement DDIV
      glsl: split DIV_TO_MUL_RCP into single- and double-precision flags
      st/glsl_to_tgsi: use DDIV instead of DRCP + DMUL

Rob Clark (8):
      freedreno: update generated headers
      freedreno/a5xx: fix cull state
      freedreno/a5xx: fix clear for uint/sint formats
      freedreno/a5xx: fix int vbos
      freedreno/a5xx: srgb fix
      freedreno/a5xx: fix psize
      freedreno/a5xx: set fragcoordxy properly
      freedreno/a5xx: set frag shader threadsize

Samuel Pitoiset (1):
      gallium/hud: add missing break in hud_cpufreq_graph_install()

Topi Pohjolainen (4):
      i965/blorp: Use the render cache mechanism instead of explicit flushing
      i965: Make depth clear flushing more explicit
      i965/gen6: Issue direct depth stall and flush after depth clear
      i965/blorp: Make post draw flush more explicit

Zachary Michaels (1):
      radeonsi: Always leave poly_offset in a valid state

git tag: mesa-17.0.0-rc2

MD5:  de8cc5fc5b0552ff323ddcf8d39da4b8  mesa-17.0.0-rc2.tar.gz
SHA1: b459b37bf0191e851174d9b8af68981341049875  mesa-17.0.0-rc2.tar.gz
SHA256: 13734cc07c0ea4314990be96c40be937520de13de2097f04239e48047bb5f25b
PGP:  https://mesa.freedesktop.org/archive/mesa-17.0.0-rc2.tar.gz.sig

MD5:  a7f74fabcdbc8c9c0757d3ca30e76a87  mesa-17.0.0-rc2.tar.xz
SHA1: c4c44af5046b717b737e70a84b8ce62595123ba8  mesa-17.0.0-rc2.tar.xz
SHA256: 1788e124c0198cb76e0409aaf883855861d2c697ee895a84137026fffa62aba4
PGP:  https://mesa.freedesktop.org/archive/mesa-17.0.0-rc2.tar.xz.sig

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