[Mesa-announce] [ANNOUNCE] mesa 17.3.0-rc5

Emil Velikov emil.l.velikov at gmail.com
Mon Nov 20 14:40:18 UTC 2017

The fifth release candidate for Mesa 17.3.0 is now available.
This is the last planned release candidate before the final release.

We still have a couple of regressions in our tracker [1] although I'm
anticipating for those to be resolved by EOW.

[1] https://bugs.freedesktop.org/show_bug.cgi?id=103491

Adam Jackson (2):
      glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
      glx/dri3: Fix passing renderType into glXCreateContext

Alex Smith (2):
      spirv: Use correct type for sampled images
      nir/spirv: tg4 requires a sampler

Anuj Phogat (2):
      i965: Program DWord Length in MI_FLUSH_DW
      i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW

Bas Nieuwenhuizen (2):
      radv: Free syncobj with multiple imports.
      radv: Free temporary syncobj after waiting on it.

Dave Airlie (2):
      r600/shader: reserve first register of vertex shader.
      r600: fix isoline tess factor component swapping.

Derek Foreman (1):
      egl/wayland: Add a fallback when fourcc query isn't supported

Emil Velikov (2):
      meson: explicitly disable the build system for 17.3.x
      Update version to 17.3.0-rc5

Jason Ekstrand (7):
      intel/blorp: Use mocs.tex for depth stencil
      anv/blorp: Add a device parameter to blorp_surf_for_anv_image
      intel/blorp: Make the MOCS setting part of blorp_address
      i965: Use PTE MOCS for all external buffers
      i965: Add stencil buffers to cache set regardless of stencil texturing
      anv/cmd_buffer: Advance the address when initializing clear colors
      anv/cmd_buffer: Take bo_offset into account in fast clear state addresses

Kenneth Graunke (4):
      i965: Implement another VF cache invalidate workaround on Gen8+.
      i965: Upload invariant state once at the start of the batch on Gen4-5.
      intel/tools: Fix detection of enabled shader stages.
      i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.

Matt Turner (3):
      i965/fs: Fix extract_i8/u8 to a 64-bit destination
      i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
      Revert "intel/fs: Use a pure vertical stride for large register strides"

Nicolai Hähnle (1):
      tgsi/exec: fix LDEXP in softpipe

Thomas Hellstrom (1):
      loader/dri3: Improve dri3 thread-safety

Tim Rowley (2):
      swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
      swr/rast: Faster emulated simd16 permute

git tag: mesa-17.3.0-rc5

MD5:  a72b38bd13a77f5d66976ddae3a91134  mesa-17.3.0-rc5.tar.gz
SHA1: 551929fbf297680e25c529c1b077f94cc011369a  mesa-17.3.0-rc5.tar.gz
SHA256: a7ba85677bcb4777e3f14f2a360134115947b5f16408bb42258ab1cb8e31b161
SHA512: de8e0531fd281107950c23609261543f4be5a04b10a4ba8fc24189620c8bd585c89017ed43fb377fbf5973b006a664a9c7e108e546a72c61550eb187f37e0d9f
PGP:  https://mesa.freedesktop.org/archive/mesa-17.3.0-rc5.tar.gz.sig

MD5:  8195ef568389a9cea42a3b8dda00373f  mesa-17.3.0-rc5.tar.xz
SHA1: 16b91023969aca02c810a62f5d9fa9574e1c4418  mesa-17.3.0-rc5.tar.xz
SHA256: c59f4e007fdac9b95168c35ec2e98d5de10ef753a90a8d3486b632ccdabaa7a0
SHA512: b53e40f39850067e97dcf9d1eb10d1f5d3a8729933057bacf3648b86ef55c43d7b2f2f5444ae8c6f1b8677c2c3fd12f7484ee08139bd388dc4cebd8dbaf28c83
PGP:  https://mesa.freedesktop.org/archive/mesa-17.3.0-rc5.tar.xz.sig

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