[Mesa-announce] [ANNOUNCE] mesa 17.2.6
agomez at igalia.com
Sat Nov 25 23:52:57 UTC 2017
Mesa 17.2.6 is now available.
In this release we have:
In Mesa Core we have included a correction to keep a program alive when
re-linking and prevent an use-after-free.
The GLSL compiler has received several fixes, including one to prevent
a SIGSEV when calling an undeclared subroutine in certain conditions
and another to mark the xfb buffers as active only if a variable uses
The SPIR-V compiler has corrected a couple of issues involving the
usage of separate images and texture/samplers.
The Intel drivers include many new fixes, specially for i965. Several
are focused on improving SIMD32 and little-core. It also includes a fix
for a GPU hang which was detected while playing HW accelerated video
The AMD drivers have also received some care. radv has seen plugged 2
memory leaks while r600 has gotten a fix through reversing the tess
factor components for isolines.
The swr driver has corrected two performance regressions, one for the
avx512 platforms and the other for the avx/avx2 platforms.
In the ddebug gallium driver we have a fix for an use-after-free.
On the EGL side, the Wayland platform of the the DRI2 drivers has
received a fix to prevent crashing in ancient systems.
GLX has also received corrections to prevent a couple of errors when
creating and binding a context in DRI3 and DRISW, respectively.
>From build and integration point of view, we have added some few more
fixes, including one to allow building libglvnd when EGL is present but
not GLX, another to enable building targets which don't need X11, such
as omx and va, when XCB is not present, and another one to be able to
specify the prefix installation for the OpenCL icd file.
Adam Jackson (2):
glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
glx/dri3: Fix passing renderType into glXCreateContext
Alex Smith (2):
spirv: Use correct type for sampled images
nir/spirv: tg4 requires a sampler
Andres Gomez (15):
docs: add sha256 checksums for 17.2.5
cherry-ignore: intel/fs: Use a pure vertical stride for large register strides
cherry-ignore: intel/nir: Use the correct indirect lowering masks in link_shaders
cherry-ignore: intel/fs: Use the original destination region for int MUL lowering
cherry-ignore: intel/fs: refactors
cherry-ignore: r600/shader: reserve first register of vertex shader.
cherry-ignore: anv/cmd_buffer: Advance the address when initializing clear colors
cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast clear state addresses
cherry-ignore: i965: Mark BOs as external when we export their handle
cherry-ignore: added 17.3 nominations.
cherry-ignore: glsl: Fix typo fragement -> fragment
cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions
cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large register strides"
Update version to 17.2.6
docs: add release notes for 17.2.6
Anuj Phogat (2):
i965: Program DWord Length in MI_FLUSH_DW
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Bas Nieuwenhuizen (2):
radv: Free syncobj with multiple imports.
radv: Free temporary syncobj after waiting on it.
Dave Airlie (1):
r600: fix isoline tess factor component swapping.
Derek Foreman (1):
egl/wayland: Add a fallback when fourcc query isn't supported
Dylan Baker (1):
autotools: Set C++ visibility flags on Intel
Emil Velikov (3):
targets/opencl: don't hardcode the icd file install to /etc/...
configure.ac: loosen --enable-glvnd check to honour egl
configure.ac: require xcb* for the omx/va/... when using x11 platform
George Barrett (1):
glsl: Catch subscripted calls to undeclared subroutines
Jason Ekstrand (9):
intel/fs: Use ANY/ALL32 predicates in SIMD32
intel/fs: Use an explicit D type for vote any/all/eq intrinsics
intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
intel/eu/reg: Add a subscript() helper
intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
intel/fs: Fix integer multiplication lowering for src/dst hazards
intel/fs: Mark 64-bit values as being contiguous
intel/fs: Rework zero-length URB write handling
i965: Add stencil buffers to cache set regardless of stencil texturing
Kenneth Graunke (5):
i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
i965: Make L3 configuration atom listen for TCS/TES program updates.
intel/tools: Fix detection of enabled shader stages.
i965: Implement another VF cache invalidate workaround on Gen8+.
i965: Upload invariant state once at the start of the batch on Gen4-5.
Matt Turner (2):
i965/fs: Fix extract_i8/u8 to a 64-bit destination
i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Neil Roberts (1):
glsl: Transform fb buffers are only active if a variable uses them
Nicolai Hähnle (1):
ddebug: fix use-after-free of streamout targets
Tim Rowley (2):
swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
swr/rast: Faster emulated simd16 permute
Timothy Arceri (3):
glsl: drop cache_fallback
glsl: use the correct parent when allocating program data members
mesa: rework how we free gl_shader_program_data
git tag: mesa-17.2.6
MD5: 7c0db6f5d6a8af7c851a482848b8a6d7 mesa-17.2.6.tar.gz
SHA1: 4306599cca04222a3426f6933412c2010f43bb42 mesa-17.2.6.tar.gz
SHA256: a9ed76702ffb14ad674ad48899f5c8c7e3a0f987911878a5dfdc4117dce5b415 mesa-17.2.6.tar.gz
SHA512: 6a646ed6513c103d08464e49355e7b0f488cf7acb0c18aa1bf9b5172df947fcd381f161737981d8b2241db1ac4ebb56165792505bcd300383be4b1ce9ebc6bb5 mesa-17.2.6.tar.gz
MD5: 862f2b7e2a08554570b192a89f723b6f mesa-17.2.6.tar.xz
SHA1: 03003f7d5966ef842d169020e95bcbdf92add055 mesa-17.2.6.tar.xz
SHA256: 6ad85224620330be26ab68c8fc78381b12b38b610ade2db8716b38faaa8f30de mesa-17.2.6.tar.xz
SHA512: 739645d963da2ff79fa0f2bfcc4948516c4f0a768f9d21f98eff049edc88218847afd3786003ccf7b10deec585f4f1d7f70fcc5e5f6e33186ebbb86cd8cb0202 mesa-17.2.6.tar.xz
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