<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Fri, Mar 17, 2017 at 11:07 AM, Emil Velikov <<a href="mailto:emil.l.velikov@gmail.com" target="_blank">emil.l.velikov@gmail.com</a>> wrote: <blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hello list, The candidate for the Mesa 17.0.2 is now available. Currently we have: - 42 queued - 3 nominated (outstanding) - and 1 rejected patch(es) Current queue consists predominantly of ANV and RADV fixes. The i965, nouveau (nvc0) and radeons has also seen some Improvements. To top it up we have a build fix for the clover (OpenCL) state-tracker. Take a look at section "Mesa stable queue" for more information. Testing reports/general approval -------------------------------- Any testing reports (or general approval of the state of the branch) will be greatly appreciated. The plan is to have 17.0.2 this Friday (19th of March), around or shortly after 18:00 GMT. If you have any questions or suggestions - be that about the current patch queue or otherwise, please go ahead. Trivial merge conflicts ----------------------- commit 7f7b1160d48d5215aaa8a3826f3c37aa8c3d5c2c Author: Emil Velikov <<a href="mailto:emil.velikov@collabora.com">emil.velikov@collabora.com</a>> i965: move brw_define.h ifndef guard to the top (cherry picked from commit 077078ce77e8653725def01ed291eb486989a9ad) commit ed5c3fad3778d338f0f886e87381bd9e1d3737cf Author: Dave Airlie <<a href="mailto:airlied@redhat.com">airlied@redhat.com</a>> radv: setup llvm target data layout (cherry picked from commit b8ee70384adc3286d18febba7a92047118cc0f0f) commit 0d7d4f973d17d74ea9a177c09a0b70bf7370b190 Author: Nanley Chery <<a href="mailto:nanley.g.chery@intel.com">nanley.g.chery@intel.com</a>> anv/image: Remove extra dependency on HiZ-specific variable (cherry picked from commit 258af3a856328934d30b7cdf626d5fdba76852f2) commit 74c39635b8a9341c2607c11373fac590eca0f689 Author: Samuel Pitoiset <<a href="mailto:samuel.pitoiset@gmail.com">samuel.pitoiset@gmail.com</a>> radeonsi: disable sinking common instructions down to the end block (cherry picked from commit 7751ed39e40e08e5aa0633d018c9f25ad17f9bb0) Cheers, Emil Mesa stable queue ----------------- Nominated (3) ============= Jason Ekstrand (2): 8184013 anv/query: Invalidate the correct range 08df015 anv/GetQueryPoolResults: Actually implement the spec </blockquote><div> </div><div>These landed yesterday. We also want 4bbb4b95b8ba02693f5e6990b983ebb66dc6241a in stable (landed yesterday). </div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> Topi Pohjolainen (1): bd25d96 i965/gen8+: Do full stall when switching pipeline Queued (42) =========== Alex Smith (3): radv: Emit pending flushes before executing a secondary command buffer radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer radv/ac: Fix shared memory offset calculation Bas Nieuwenhuizen (3): radv: Disable HTILE for textures with multiple layers/levels. radv: Emit cache flushes before CP DMA. Revert "radv: Emit cache flushes before CP DMA." Dave Airlie (3): radv: drop Z24 support. radv: disable mip point pre clamping. radv: setup llvm target data layout Emil Velikov (2): cherry-ignore: add the swizzle blorp_clear fix i965: move brw_define.h ifndef guard to the top Fredrik Höglund (2): radv: fix the dynamic buffer index in vkCmdBindDescriptorSets radv/ac: fix multiple descriptor sets with dynamic buffers Gregory Hainaut (1): glapi: fix typo in count_scale Ilia Mirkin (2): nvc0: take extra pushbuf space into account for pushbuf_space calls nvc0: increase alignment to 256 for texture buffers on fermi Jacob Lifshay (1): vulkan/wsi: Improve the DRI3 error message James Legg (1): radv: Fix using more than 4 bound descriptor sets Jason Ekstrand (7): anv/blorp/clear_subpass: Only set surface clear color for fast clears anv: Accurately advertise dynamic descriptor limits anv: Stall before fast-clear operations anv: Properly handle destroying NULL devices and instances anv/blorp: Turn off AUX after doing a CCS_D resolve anv/blorp: Only set a clear color for resolves if fast-cleared nir/intrinsics: Make load_barycentric_input take a 2-component coor Jonas Pfeil (1): ralloc: Make sure ralloc() allocations match malloc()'s alignment. Kenneth Graunke (1): egl: Ensure ResetNotificationStrategy matches for shared contexts. Marek Olšák (3): st/mesa: reset sample_mask, min_sample, and render_condition for PBO ops st/mesa: set blend state for PBO readbacks radeonsi: mark all bound shader buffer ranges as initialized Matt Turner (1): clover: Work around build failure with AltiVec. Nanley Chery (2): anv/pass: Avoid accessing attachment array out of bounds anv/image: Remove extra dependency on HiZ-specific variable Nicolai Hähnle (2): st/glsl_to_tgsi: avoid iterating past the head of the instruction list st/mesa: inform the driver of framebuffer changes before compute dispatches Robert Foss (1): mesa: Avoid read of uninitialized variable Samuel Iglesias Gonsálvez (5): i965/fs: mark last DF uniform array element as 64 bit live one i965/fs: detect different bit size accesses to uniforms to push them in proper locations i965/fs: fix indirect load DF uniforms on BSW/BXT i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles i965/fs: emit MOV_INDIRECT with the source with the right register type Samuel Pitoiset (1): radeonsi: disable sinking common instructions down to the end block Rejected (1) ============ Jason Ekstrand (1): d49d275 anv/blorp: Don't sanitize the swizzle for blorp_clear Reason: commit addresses an earlier one [ccdd5b3738e] which is missing in branch. _______________________________________________ mesa-dev mailing list <a href="mailto:mesa-dev@lists.freedesktop.org">mesa-dev@lists.freedesktop.org</a> <a href="https://lists.freedesktop.org/mailman/listinfo/mesa-dev" rel="noreferrer" target="_blank">https://lists.freedesktop.org/mailman/listinfo/mesa-dev</a> </blockquote></div> </div></div>