mesa: Branch 'master' - 5 commits
Keith Packard
keithp at kemper.freedesktop.org
Sat Jan 6 23:37:33 UTC 2007
src/mesa/drivers/dri/i965/brw_clip.c | 2
src/mesa/drivers/dri/i965/brw_eu.h | 1
src/mesa/drivers/dri/i965/brw_eu_emit.c | 155 ++++++++++++++++---------
src/mesa/drivers/dri/i965/brw_exec_api.c | 12 +
src/mesa/drivers/dri/i965/brw_gs.c | 4
src/mesa/drivers/dri/i965/brw_structs.h | 22 +++
src/mesa/drivers/dri/i965/brw_wm_state.c | 2
src/mesa/drivers/dri/i965/bufmgr.h | 2
src/mesa/drivers/dri/i965/bufmgr_fake.c | 16 ++
src/mesa/drivers/dri/i965/intel_blit.c | 4
src/mesa/drivers/dri/i965/intel_context.c | 34 +++++
src/mesa/drivers/dri/i965/intel_context.h | 1
src/mesa/drivers/dri/i965/intel_ioctl.c | 32 ++++-
src/mesa/drivers/dri/i965/server/i830_common.h | 19 +++
14 files changed, 239 insertions(+), 67 deletions(-)
New commits:
diff-tree ef02f8be10a9f95788fee48bb9e7801dea0c2ba6 (from 652ae2c3765a471f94ca7b7328a0d572182bb127)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Wed Dec 13 15:27:17 2006 +0800
i965: xdemos/glxthreads get: Assertion `block->fenced' failed (9201)
Signed-off-by: Keith Packard <keithp at neko.keithp.com>
diff --git a/src/mesa/drivers/dri/i965/bufmgr.h b/src/mesa/drivers/dri/i965/bufmgr.h
index 6932522..e748c0d 100644
--- a/src/mesa/drivers/dri/i965/bufmgr.h
+++ b/src/mesa/drivers/dri/i965/bufmgr.h
@@ -199,9 +199,11 @@ void *bmFindVirtual( struct intel_contex
* For now they can stay, but will likely change/move before final:
*/
unsigned bmSetFence( struct intel_context * );
+unsigned bmSetFenceLock( struct intel_context * );
unsigned bmLockAndFence( struct intel_context *intel );
int bmTestFence( struct intel_context *, unsigned fence );
void bmFinishFence( struct intel_context *, unsigned fence );
+void bmFinishFenceLock( struct intel_context *, unsigned fence );
void bm_fake_NotifyContendedLockTake( struct intel_context * );
diff --git a/src/mesa/drivers/dri/i965/bufmgr_fake.c b/src/mesa/drivers/dri/i965/bufmgr_fake.c
index ed88ab3..205dc72 100644
--- a/src/mesa/drivers/dri/i965/bufmgr_fake.c
+++ b/src/mesa/drivers/dri/i965/bufmgr_fake.c
@@ -338,7 +338,6 @@ static int evict_mru( struct intel_conte
}
-
static int check_fenced( struct intel_context *intel )
{
struct bufmgr *bm = intel->bm;
@@ -1328,11 +1327,19 @@ unsigned bmSetFence( struct intel_contex
return intel->bm->last_fence;
}
+unsigned bmSetFenceLock( struct intel_context *intel )
+{
+ LOCK(intel->bm);
+ bmSetFence(intel);
+ UNLOCK(intel->bm);
+}
unsigned bmLockAndFence( struct intel_context *intel )
{
if (intel->bm->need_fence) {
LOCK_HARDWARE(intel);
+ LOCK(intel->bm);
bmSetFence(intel);
+ UNLOCK(intel->bm);
UNLOCK_HARDWARE(intel);
}
@@ -1350,7 +1357,12 @@ void bmFinishFence( struct intel_context
check_fenced(intel);
}
-
+void bmFinishFenceLock( struct intel_context *intel, unsigned fence )
+{
+ LOCK(intel->bm);
+ bmFinishFence(intel, fence);
+ UNLOCK(intel->bm);
+}
/* Specifically ignore texture memory sharing.
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index c8c5bf9..173d1d5 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -66,7 +66,7 @@ void intelCopyBuffer( const __DRIdrawabl
intelFlush( &intel->ctx );
- bmFinishFence(intel, intel->last_swap_fence);
+ bmFinishFenceLock(intel, intel->last_swap_fence);
/* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
* should work regardless.
@@ -155,7 +155,7 @@ void intelCopyBuffer( const __DRIdrawabl
intel_batchbuffer_flush( intel->batch );
intel->second_last_swap_fence = intel->last_swap_fence;
- intel->last_swap_fence = bmSetFence( intel );
+ intel->last_swap_fence = bmSetFenceLock( intel );
UNLOCK_HARDWARE( intel );
if (!rect)
diff-tree 652ae2c3765a471f94ca7b7328a0d572182bb127 (from 4068e2d1b766a9ccedcb8d7cd07c49d22dff39f0)
Author: Zou Nan hai <nanhai.zou at intel.com>
Date: Tue Dec 12 15:00:27 2006 +0800
i965: Take clip rects into account when computing max prim
Signed-off-by: Keith Packard <keithp at neko.keithp.com>
diff --git a/src/mesa/drivers/dri/i965/brw_exec_api.c b/src/mesa/drivers/dri/i965/brw_exec_api.c
index 470fa6f..8b243c6 100644
--- a/src/mesa/drivers/dri/i965/brw_exec_api.c
+++ b/src/mesa/drivers/dri/i965/brw_exec_api.c
@@ -42,6 +42,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "dispatch.h"
#include "brw_exec.h"
+#include "intel_context.h"
+
static void reset_attrfv( struct brw_exec_context *exec );
@@ -522,6 +524,14 @@ static void GLAPIENTRY brw_exec_Begin( G
}
+static GLuint brw_max_prim( GLcontext *ctx )
+{
+ struct intel_context *intel = intel_context( ctx );
+ if (intel->numClipRects <= 1)
+ return BRW_MAX_PRIM;
+ return BRW_MAX_PRIM/intel->numClipRects;
+}
+
static void GLAPIENTRY brw_exec_End( void )
{
GET_CURRENT_CONTEXT( ctx );
@@ -536,7 +546,7 @@ static void GLAPIENTRY brw_exec_End( voi
ctx->Driver.CurrentExecPrimitive = GL_POLYGON+1;
- if (exec->vtx.prim_count == BRW_MAX_PRIM)
+ if (exec->vtx.prim_count >= brw_max_prim(ctx))
brw_exec_vtx_flush( exec );
}
else
diff-tree 4068e2d1b766a9ccedcb8d7cd07c49d22dff39f0 (from 1b9f78195f62959601d440475a6cbba5e8046813)
Author: Wang Zhenyu <zhenyu.z.wang at intel.com>
Date: Mon Dec 11 00:01:56 2006 -0800
i965: ARB_occlusion_query support
Signed-off-by: Keith Packard <keithp at neko.keithp.com>
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 4707a70..e41042d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -168,7 +168,7 @@ static void upload_wm_unit(struct brw_co
wm.wm5.line_stipple = 1;
}
- if (INTEL_DEBUG & DEBUG_STATS)
+ if (INTEL_DEBUG & DEBUG_STATS || intel->stats_wm)
wm.wm4.stats_enable = 1;
brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 5e97e4d..9acafe5 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -70,6 +70,7 @@ int INTEL_DEBUG = (0);
#define need_GL_ARB_vertex_buffer_object
#define need_GL_ARB_vertex_program
#define need_GL_ARB_window_pos
+#define need_GL_ARB_occlusion_query
#define need_GL_EXT_blend_color
#define need_GL_EXT_blend_equation_separate
#define need_GL_EXT_blend_func_separate
@@ -157,6 +158,7 @@ const struct dri_extension card_extensio
{ "GL_ARB_vertex_buffer_object", GL_ARB_vertex_buffer_object_functions },
{ "GL_ARB_vertex_program", GL_ARB_vertex_program_functions },
{ "GL_ARB_window_pos", GL_ARB_window_pos_functions },
+ { "GL_ARB_occlusion_query", GL_ARB_occlusion_query_functions},
{ "GL_EXT_blend_color", GL_EXT_blend_color_functions },
{ "GL_EXT_blend_equation_separate", GL_EXT_blend_equation_separate_functions },
{ "GL_EXT_blend_func_separate", GL_EXT_blend_func_separate_functions },
@@ -241,6 +243,36 @@ void intelFinish( GLcontext *ctx )
bmFinishFence(intel, bmLockAndFence(intel));
}
+static void
+intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+ struct intel_context *intel = intel_context( ctx );
+ GLuint64EXT tmp = 0;
+ drmI830MMIO io = {
+ .read_write = MMIO_WRITE,
+ .reg = MMIO_REGS_PS_DEPTH_COUNT,
+ .data = &tmp
+ };
+ intel->stats_wm = GL_TRUE;
+ intelFinish(&intel->ctx);
+ drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+}
+
+static void
+intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+ struct intel_context *intel = intel_context( ctx );
+ drmI830MMIO io = {
+ .read_write = MMIO_READ,
+ .reg = MMIO_REGS_PS_DEPTH_COUNT,
+ .data = &q->Result
+ };
+ intelFinish(&intel->ctx);
+ drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+ q->Ready = GL_TRUE;
+ intel->stats_wm = GL_FALSE;
+}
+
void intelInitDriverFunctions( struct dd_function_table *functions )
{
@@ -250,6 +282,8 @@ void intelInitDriverFunctions( struct dd
functions->Finish = intelFinish;
functions->GetString = intelGetString;
functions->UpdateState = intelInvalidateState;
+ functions->BeginQuery = intelBeginQuery;
+ functions->EndQuery = intelEndQuery;
/* CopyPixels can be accelerated even with the current memory
* manager:
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 8367a95..fe7ee38 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -177,6 +177,7 @@ struct intel_context
GLuint second_last_swap_fence;
GLboolean aub_wrap;
+ GLboolean stats_wm;
struct intel_batchbuffer *batch;
diff --git a/src/mesa/drivers/dri/i965/server/i830_common.h b/src/mesa/drivers/dri/i965/server/i830_common.h
index e3bbdc7..f320378 100644
--- a/src/mesa/drivers/dri/i965/server/i830_common.h
+++ b/src/mesa/drivers/dri/i965/server/i830_common.h
@@ -52,6 +52,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DRM_I830_INIT_HEAP 0x0a
#define DRM_I830_CMDBUFFER 0x0b
#define DRM_I830_DESTROY_HEAP 0x0c
+#define DRM_I830_MMIO 0x10
typedef struct {
enum {
@@ -199,5 +200,23 @@ typedef struct {
int region;
} drmI830MemDestroyHeap;
+#define MMIO_READ 0
+#define MMIO_WRITE 1
+
+#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
+#define MMIO_REGS_IA_VERTICES_COUNT 1
+#define MMIO_REGS_VS_INVOCATION_COUNT 2
+#define MMIO_REGS_GS_PRIMITIVES_COUNT 3
+#define MMIO_REGS_GS_INVOCATION_COUNT 4
+#define MMIO_REGS_CL_PRIMITIVES_COUNT 5
+#define MMIO_REGS_CL_INVOCATION_COUNT 6
+#define MMIO_REGS_PS_INVOCATION_COUNT 7
+#define MMIO_REGS_PS_DEPTH_COUNT 8
+
+typedef struct {
+ unsigned int read_write:1;
+ unsigned int reg:31;
+ void __user *data;
+} drmI830MMIO;
#endif /* _I830_DRM_H_ */
diff-tree 1b9f78195f62959601d440475a6cbba5e8046813 (from e54ec49155052ab663d8671e7036d985992464a3)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Oct 18 00:24:01 2006 -0700
i965: Avoid branch instructions while in single program flow mode.
There is an errata for Broadwater that threads don't have the instruction/loop
mask stacks initialized on thread spawn. In single program flow mode, those
stacks are not writable, so we can't initialize them. However, they do get
read during ELSE and ENDIF instructions. So, instead, replace branch
instructions in single program flow mode with predicated jumps (ADD to the ip
register), avoiding use of the more complicated branch instructions that may
fail. This is also a minor optimization as no ENDIF equivalent is necessary.
Signed-off-by: Keith Packard <keithp at neko.keithp.com>
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 0e8591a..3bec153 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -62,6 +62,8 @@ static void compile_clip_prog( struct br
*/
brw_init_compile(&c.func);
+ c.func.single_program_flow = 1;
+
c.key = *key;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 1afa0f8..d4dbcf3 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -104,6 +104,7 @@ struct brw_compile {
struct brw_instruction *current;
GLuint flag_value;
+ GLboolean single_program_flow;
};
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 6425c91..9992b47 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -464,7 +464,6 @@ struct brw_instruction *brw_JMPI(struct
return insn;
}
-
/* EU takes the value from the flag register and pushes it onto some
* sort of a stack (presumably merging with any flag value already on
* the stack). Within an if block, the flags at the top of the stack
@@ -482,7 +481,16 @@ struct brw_instruction *brw_JMPI(struct
*/
struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_IF);
+ struct brw_instruction *insn;
+
+ if (p->single_program_flow) {
+ assert(execute_size == BRW_EXECUTE_1);
+
+ insn = next_insn(p, BRW_OPCODE_ADD);
+ insn->header.predicate_inverse = 1;
+ } else {
+ insn = next_insn(p, BRW_OPCODE_IF);
+ }
/* Override the defaults for this instruction:
*/
@@ -504,7 +512,13 @@ struct brw_instruction *brw_IF(struct br
struct brw_instruction *brw_ELSE(struct brw_compile *p,
struct brw_instruction *if_insn)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ELSE);
+ struct brw_instruction *insn;
+
+ if (p->single_program_flow) {
+ insn = next_insn(p, BRW_OPCODE_ADD);
+ } else {
+ insn = next_insn(p, BRW_OPCODE_ELSE);
+ }
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
@@ -516,11 +530,17 @@ struct brw_instruction *brw_ELSE(struct
/* Patch the if instruction to point at this instruction.
*/
- assert(if_insn->header.opcode == BRW_OPCODE_IF);
+ if (p->single_program_flow) {
+ assert(if_insn->header.opcode == BRW_OPCODE_ADD);
- if_insn->bits3.if_else.jump_count = insn - if_insn;
- if_insn->bits3.if_else.pop_count = 1;
- if_insn->bits3.if_else.pad0 = 0;
+ if_insn->bits3.ud = (insn - if_insn + 1) * 16;
+ } else {
+ assert(if_insn->header.opcode == BRW_OPCODE_IF);
+
+ if_insn->bits3.if_else.jump_count = insn - if_insn;
+ if_insn->bits3.if_else.pop_count = 1;
+ if_insn->bits3.if_else.pad0 = 0;
+ }
return insn;
}
@@ -528,63 +548,76 @@ struct brw_instruction *brw_ELSE(struct
void brw_ENDIF(struct brw_compile *p,
struct brw_instruction *patch_insn)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
+ if (p->single_program_flow) {
+ /* In single program flow mode, there's no need to execute an ENDIF,
+ * since we don't need to do any stack operations, and if we're executing
+ * currently, we want to just continue executing.
+ */
+ struct brw_instruction *next = &p->store[p->nr_insn];
- brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src1(insn, brw_imm_d(0x0));
+ assert(patch_insn->header.opcode == BRW_OPCODE_ADD);
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.execution_size = patch_insn->header.execution_size;
- insn->header.mask_control = BRW_MASK_ENABLE;
+ patch_insn->bits3.ud = (next - patch_insn) * 16;
+ } else {
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
- assert(patch_insn->bits3.if_else.jump_count == 0);
-
- /* Patch the if or else instructions to point at this or the next
- * instruction respectively.
- */
- if (patch_insn->header.opcode == BRW_OPCODE_IF) {
- /* Automagically turn it into an IFF:
+ brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src1(insn, brw_imm_d(0x0));
+
+ insn->header.compression_control = BRW_COMPRESSION_NONE;
+ insn->header.execution_size = patch_insn->header.execution_size;
+ insn->header.mask_control = BRW_MASK_ENABLE;
+
+ assert(patch_insn->bits3.if_else.jump_count == 0);
+
+ /* Patch the if or else instructions to point at this or the next
+ * instruction respectively.
*/
- patch_insn->header.opcode = BRW_OPCODE_IFF;
- patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
- patch_insn->bits3.if_else.pop_count = 0;
- patch_insn->bits3.if_else.pad0 = 0;
+ if (patch_insn->header.opcode == BRW_OPCODE_IF) {
+ /* Automagically turn it into an IFF:
+ */
+ patch_insn->header.opcode = BRW_OPCODE_IFF;
+ patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
+ patch_insn->bits3.if_else.pop_count = 0;
+ patch_insn->bits3.if_else.pad0 = 0;
+ } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
+ patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
+ patch_insn->bits3.if_else.pop_count = 1;
+ patch_insn->bits3.if_else.pad0 = 0;
+ } else {
+ assert(0);
+ }
+ /* Also pop item off the stack in the endif instruction:
+ */
+ insn->bits3.if_else.jump_count = 0;
+ insn->bits3.if_else.pop_count = 1;
+ insn->bits3.if_else.pad0 = 0;
}
- else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
- patch_insn->bits3.if_else.jump_count = insn - patch_insn + 1;
- patch_insn->bits3.if_else.pop_count = 1;
- patch_insn->bits3.if_else.pad0 = 0;
- }
- else {
- assert(0);
- }
-
- /* Also pop item off the stack in the endif instruction:
- */
- insn->bits3.if_else.jump_count = 0;
- insn->bits3.if_else.pop_count = 1;
- insn->bits3.if_else.pad0 = 0;
}
/* DO/WHILE loop:
*/
struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
+ if (p->single_program_flow) {
+ return &p->store[p->nr_insn];
+ } else {
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
- /* Override the defaults for this instruction:
- */
- brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
- brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+ /* Override the defaults for this instruction:
+ */
+ brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
+ brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
- insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.execution_size = execute_size;
-/* insn->header.mask_control = BRW_MASK_ENABLE; */
+ insn->header.compression_control = BRW_COMPRESSION_NONE;
+ insn->header.execution_size = execute_size;
+ /* insn->header.mask_control = BRW_MASK_ENABLE; */
- return insn;
+ return insn;
+ }
}
@@ -592,19 +625,31 @@ struct brw_instruction *brw_DO(struct br
void brw_WHILE(struct brw_compile *p,
struct brw_instruction *do_insn)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WHILE);
+ struct brw_instruction *insn;
+
+ if (p->single_program_flow)
+ insn = next_insn(p, BRW_OPCODE_ADD);
+ else
+ insn = next_insn(p, BRW_OPCODE_WHILE);
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
- insn->header.execution_size = do_insn->header.execution_size;
- assert(do_insn->header.opcode == BRW_OPCODE_DO);
- insn->bits3.if_else.jump_count = do_insn - insn;
- insn->bits3.if_else.pop_count = 0;
- insn->bits3.if_else.pad0 = 0;
+ if (p->single_program_flow) {
+ insn->header.execution_size = BRW_EXECUTE_1;
+
+ insn->bits3.d = (do_insn - insn) * 16;
+ } else {
+ insn->header.execution_size = do_insn->header.execution_size;
+
+ assert(do_insn->header.opcode == BRW_OPCODE_DO);
+ insn->bits3.if_else.jump_count = do_insn - insn;
+ insn->bits3.if_else.pop_count = 0;
+ insn->bits3.if_else.pad0 = 0;
+ }
/* insn->header.mask_control = BRW_MASK_ENABLE; */
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 7d3f9dd..9066e42 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -66,7 +66,9 @@ static void compile_gs_prog( struct brw_
/* Begin the compilation:
*/
brw_init_compile(&c.func);
-
+
+ c.func.single_program_flow = 1;
+
/* For some reason the thread is spawned with only 4 channels
* unmasked.
*/
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 25acdcf..10fee94 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -519,7 +519,22 @@ struct thread3
struct brw_clip_unit_state
{
struct thread0 thread0;
- struct thread1 thread1;
+ struct
+ {
+ GLuint pad0:7;
+ GLuint sw_exception_enable:1;
+ GLuint pad1:3;
+ GLuint mask_stack_exception_enable:1;
+ GLuint pad2:1;
+ GLuint illegal_op_exception_enable:1;
+ GLuint pad3:2;
+ GLuint floating_point_mode:1;
+ GLuint thread_priority:1;
+ GLuint binding_table_entry_count:8;
+ GLuint pad4:5;
+ GLuint single_program_flow:1;
+ } thread1;
+
struct thread2 thread2;
struct thread3 thread3;
@@ -532,8 +547,8 @@ struct brw_clip_unit_state
GLuint pad1:1;
GLuint urb_entry_allocation_size:5;
GLuint pad2:1;
- GLuint max_threads:6; /* may be less */
- GLuint pad3:1;
+ GLuint max_threads:1; /* may be less */
+ GLuint pad3:6;
} thread4;
struct
@@ -1322,6 +1337,7 @@ struct brw_instruction
GLuint end_of_thread:1;
} generic;
+ GLint d;
GLuint ud;
} bits3;
};
diff-tree e54ec49155052ab663d8671e7036d985992464a3 (from f1fbaf39ff9b818c17c3a3f35e9517b4d826ec61)
Author: Eric Anholt <eric at anholt.net>
Date: Wed Oct 11 12:16:09 2006 -0700
i965: Connect INTEL_DEBUG=sync up to cmd/batch ioctls.
Signed-off-by: Keith Packard <keithp at neko.keithp.com>
diff --git a/src/mesa/drivers/dri/i965/intel_ioctl.c b/src/mesa/drivers/dri/i965/intel_ioctl.c
index f3b76db..4da3127 100644
--- a/src/mesa/drivers/dri/i965/intel_ioctl.c
+++ b/src/mesa/drivers/dri/i965/intel_ioctl.c
@@ -43,6 +43,26 @@
#include "drm.h"
#include "bufmgr.h"
+static int intelWaitIdleLocked( struct intel_context *intel )
+{
+ static int in_wait_idle = 0;
+ unsigned int fence;
+
+ if (!in_wait_idle) {
+ if (INTEL_DEBUG & DEBUG_SYNC) {
+ fprintf(stderr, "waiting for idle\n");
+ }
+
+ in_wait_idle = 1;
+ fence = bmSetFence(intel);
+ intelWaitIrq(intel, fence);
+ in_wait_idle = 0;
+
+ return bmTestFence(intel, fence);
+ } else {
+ return 1;
+ }
+}
int intelEmitIrqLocked( struct intel_context *intel )
{
@@ -140,7 +160,11 @@ void intel_batch_ioctl( struct intel_con
UNLOCK_HARDWARE(intel);
exit(1);
}
- }
+
+ if (INTEL_DEBUG & DEBUG_SYNC) {
+ intelWaitIdleLocked(intel);
+ }
+ }
}
void intel_cmd_ioctl( struct intel_context *intel,
@@ -172,5 +196,9 @@ void intel_cmd_ioctl( struct intel_conte
UNLOCK_HARDWARE(intel);
exit(1);
}
- }
+
+ if (INTEL_DEBUG & DEBUG_SYNC) {
+ intelWaitIdleLocked(intel);
+ }
+ }
}
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