mesa: Branch 'master'

[Ben Skeggs]

 src/mesa/drivers/dri/nouveau/nouveau_shader_0.c |   24 ++++++++++++++++++++++++
 1 files changed, 24 insertions(+)

New commits:
diff-tree 60c28739aa4afe543e0293c15a7aaf84ec2183ea (from cf33bcf0b246f75094673beaa989034fa27c4b9f)
Author: Ben Skeggs <darktama at iinet.net.au>
Date:   Tue Jan 23 16:25:25 2007 +1100

    nouveau: DPH and CMP for NV40 which doesn't do it natively.

diff --git a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c b/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c
index 3e542ea..28c6ad8 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_shader_0.c
@@ -594,6 +594,30 @@ pass0_emulate_instruction(nouveauShader 
 			ARITH(NVS_OP_MAX, dest, mask, sat,
 					src[0], nvsNegate(src[0]), nvr_unused);
 		break;
+	case OPCODE_CMP:
+		/*XXX: this will clobber CC0... */
+		ARITH (NVS_OP_MOV, dest, mask, sat,
+				src[2], nvr_unused, nvr_unused);
+		pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
+		ARITHu(NVS_OP_MOV, temp, SMASK_ALL, 0,
+				src[0], nvr_unused, nvr_unused);
+		nvsinst->cond_update = 1;
+		nvsinst->cond_reg    = 0;
+		ARITH (NVS_OP_MOV, dest, mask, sat,
+				src[1], nvr_unused, nvr_unused);
+		nvsinst->cond      = COND_LT;
+		nvsinst->cond_reg  = 0;
+		nvsinst->cond_test = 1;
+		break;
+	case OPCODE_DPH:
+		pass0_make_reg(nvs, &temp, NVS_FILE_TEMP, -1);
+		ARITHu(NVS_OP_DP3, temp, SMASK_X, 0,
+				 src[0], src[1], nvr_unused);
+		ARITH (NVS_OP_ADD, dest, mask, sat,
+				 nvsSwizzle(temp, X, X, X, X),
+				 nvsSwizzle(src[1], W, W, W, W),
+				 nvr_unused);
+		break;
 	case OPCODE_KIL:
 		/* This is only in ARB shaders, so we don't have to worry
 		 * about clobbering a CC reg as they aren't supported anyway.