mesa: Changes to 'master'

Eric Anholt anholt at
Fri Nov 16 15:38:56 PST 2007

 src/mesa/drivers/dri/common/dri_bufmgr.h       |   37 +++
 src/mesa/drivers/dri/common/dri_bufmgr_fake.c  |  262 ++++++++++++++++++-------
 src/mesa/drivers/dri/i915/intel_context.c      |    1 
 src/mesa/drivers/dri/i915/intel_context.h      |    1 
 src/mesa/drivers/dri/i915/intel_tris.c         |    3 
 src/mesa/drivers/dri/intel/intel_batchbuffer.c |   14 -
 src/mesa/drivers/dri/intel/intel_buffers.c     |  154 ++++++--------
 src/mesa/drivers/dri/intel/intel_chipset.h     |   12 -
 8 files changed, 319 insertions(+), 165 deletions(-)

commit diffs at;a=summary

New commits:
commit a66413874dd50512daf10ce6254bbafd14b61ac7
Author: Eric Anholt <eric at>
Date:   Fri Nov 16 15:01:48 2007 -0800

    [intel] Fix typos in intel_chipset.h macros.

commit 3bd07ba0d4f759e3a17e2a5ed51086b44705a482
Author: Eric Anholt <eric at>
Date:   Fri Nov 16 14:56:26 2007 -0800

    [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.

commit f7e0513d700167a7eff39e40c855027096f1db1d
Author: Eric Anholt <eric at>
Date:   Thu Oct 25 11:31:15 2007 -0700

    [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.

commit 152aa6350d473128422991342c0a4509f4b37bc6
Author: Eric Anholt <eric at>
Date:   Thu Nov 15 14:00:17 2007 -0800

    [intel] Add some doxygen notes on what the bufmgr_fake block members mean.

commit c29e9e534ee2138d0fb26d5b1cf215bfcf5fc9ef
Author: Eric Anholt <eric at>
Date:   Fri Nov 16 14:45:26 2007 -0800

    [intel] Add a simple relocation cache to the fake buffer manager.
    This is required for 965 performance, as it avoids a lot of repeated data
    uploads of the state caches due to surface offsets in them.

commit 4bc625e378dfc290af89ccc353e8b90ae734ccd0
Author: Eric Anholt <eric at>
Date:   Fri Nov 16 14:38:09 2007 -0800

    [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.
    They shouldn't be created, and this often helps catch stupid issues.

commit 00eb5635c6e0a41524c55f450a6a9ce8ba5d6be8
Author: Eric Anholt <eric at>
Date:   Fri Nov 16 14:20:24 2007 -0800

    [intel] Add support for multiple levels of relocation in bufmgr_fake.
    This is required for 965 support, which has relocations in other places than
    just the batchbuffer.

commit df3c530bedd0ee59e0ae5c18a916f78fd3f7559a
Author: Eric Anholt <eric at>
Date:   Fri Nov 9 16:43:21 2007 -0800

    [i915] Push locking in intelClearWithTris down inside meta_draw_poly.
    The lock coverage and checks for cliprects were unneeded since the batchbuffer
    will have INTEL_BATCH_CLIPRECTS anyway.  It appeared to be a leftover from
    This makes the locking requirements of i915 meta_draw_quad match i965

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