mesa: Changes to 'mesa_7_0_branch'

[Haihao Xiang]

The branch, mesa_7_0_branch has been updated
        Commits at: http://cgit.freedesktop.org/mesa/mesa/log/?h=mesa_7_0_branch

Summary of changes:
 src/mesa/drivers/dri/i915/intel_context.h        |    2 +
 src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c |    9 +++-
 src/mesa/drivers/dri/i965/brw_clip_state.c       |    3 +-
 src/mesa/drivers/dri/i965/brw_curbe.c            |    2 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c      |    2 +-
 src/mesa/drivers/dri/i965/brw_gs_state.c         |    3 +-
 src/mesa/drivers/dri/i965/brw_sf_state.c         |    2 +-
 src/mesa/drivers/dri/i965/brw_state_cache.c      |    2 +-
 src/mesa/drivers/dri/i965/brw_state_pool.c       |    5 +-
 src/mesa/drivers/dri/i965/brw_tex.c              |   12 ++++-
 src/mesa/drivers/dri/i965/brw_tex_layout.c       |   46 +++++++++++++++-------
 src/mesa/drivers/dri/i965/brw_vs_state.c         |    2 +-
 src/mesa/drivers/dri/i965/brw_wm_state.c         |    4 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |   12 +++++-
 src/mesa/drivers/dri/i965/bufmgr_fake.c          |    2 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c    |    4 +-
 src/mesa/drivers/dri/i965/intel_blit.c           |    3 +-
 src/mesa/drivers/dri/i965/intel_context.h        |    2 +
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c    |   21 ++++++++--
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c   |    9 +---
 src/mesa/drivers/dri/i965/intel_tex_validate.c   |   36 +++++++++++++++-
 src/mesa/drivers/dri/intel/intel_tex_layout.c    |   42 +++++++++++++++----
 src/mesa/drivers/dri/intel/intel_tex_layout.h    |    1 +
 23 files changed, 165 insertions(+), 61 deletions(-)

       via  93f2eec6b353e83d267929af68c98878c85c166b (commit)
       via  46ef09d7874d1f8226392b1059ba9642fbffe16a (commit)
       via  7487ec0ff09b140907b89c42754bc562757b2516 (commit)
       via  a25549866fb8a1fdc9fef7c595553a3e8b733d65 (commit)
       via  558cc6e38f1187558b0cf1a627d07788ef4dfc23 (commit)
      from  feb1fa1e833b817374fb2e3f3224c64be9a680d8 (commit)


- Commits -----------------------------------------------
commit 93f2eec6b353e83d267929af68c98878c85c166b
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Fri Aug 10 16:37:30 2007 +0800

    i965: roland's DXTn format texture patch(bug10347)
    
    Cherry picked from commit db928291dcbda2a820dbb1668c43d2fb4266be7c

commit 46ef09d7874d1f8226392b1059ba9642fbffe16a
Author: Eric Anholt <eric at anholt.net>
Date:   Thu Oct 4 12:07:25 2007 -0700

    [965] Replace various alignment code with a shared ALIGN() macro.
    
    In the process, fix some alignment issues:
    - Scratch space allocation was aligned into units of 1KB, while the allocation
      wanted units of bytes, so we never allocated enough space for scratch.
    - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
      ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
    
    Cherry picked from commit 77e0523fb7769df4bf43747e136b1653b2421b97

commit 7487ec0ff09b140907b89c42754bc562757b2516
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Fri Aug 17 12:42:52 2007 -0400

    i965: align width/height for volume texture
    
    Cherry picked from commit 00b86ecf6f2f936bad6d628622ea5546c780ab8d

commit a25549866fb8a1fdc9fef7c595553a3e8b733d65
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Fri Aug 10 16:23:14 2007 +0800

    intel: applying right alignment to compressed texture,
    which make small textures(4x4,2x2,1x1) work well.
    
    Cherry picked from commit 8ea66fa2ec9eeb6a7e869ff08d713f5e77d795e0

commit 558cc6e38f1187558b0cf1a627d07788ef4dfc23
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date:   Fri Aug 10 15:14:12 2007 +0800

    i965: set mt->cpp differently with compressed texture
    
    Cherry picked from commit 2cafd749b8e4fa44863c176389f7201c7f74eca9

---------------------------------