Mesa (radeon-rewrite): r300: use OUT_BATCH_REGVAL in a few more places

[Dave Airlie]

Module: Mesa
Branch: radeon-rewrite
Commit: 13ed7985b245770259681d9dc6bff16354a78be5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=13ed7985b245770259681d9dc6bff16354a78be5

Author: Dave Airlie <airlied at redhat.com>
Date:   Mon Feb 23 13:37:23 2009 +1000

r300: use OUT_BATCH_REGVAL in a few more places

---

 src/mesa/drivers/dri/r300/r300_cmdbuf.c  |   24 ++++++++++++------------
 src/mesa/drivers/dri/r300/r300_context.c |    3 +--
 2 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 29b2c2e..ac1c128 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -97,24 +97,20 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
 	addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
 	ndw = cmd.vpu.count * 4;
 	if (ndw) {
-		BEGIN_BATCH_NO_AUTOSTATE(11 + ndw);
+		BEGIN_BATCH_NO_AUTOSTATE(13 + ndw);
 
 		/* flush processing vertices */
-		OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
-		OUT_BATCH(0x0);
-		OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
-		OUT_BATCH((1 << 15) | (1 << 28));
-		OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
-		OUT_BATCH(0x00FFFFFF);
-		OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
-		OUT_BATCH(1);
-		/* write vpu */
-		OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0));
-		OUT_BATCH(addr);
+		OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
+		OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
+		OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+		OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
+		OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 1);
+		OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
 		OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
 		for (i = 0; i < ndw; i++) {
 			OUT_BATCH(atom->cmd[i+1]);
 		}
+		OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 		END_BATCH();
 	}
 }
@@ -180,6 +176,10 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
 		            END_BATCH();
 		    } else if (!t) {
 			    //assert(0);
+		            BEGIN_BATCH_NO_AUTOSTATE(4);
+		            OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
+			    OUT_BATCH(r300->radeon.radeonScreen->texOffset[0]);
+			    END_BATCH();
 		    } else {
 			    if (t->bo) {
 		            	    BEGIN_BATCH_NO_AUTOSTATE(4);
diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 6d68309..dd63add 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -238,8 +238,7 @@ static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
    BATCH_LOCALS(radeon);
    cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
    BEGIN_BATCH_NO_AUTOSTATE(2);
-   OUT_BATCH(cmdpacket0(radeon->radeonScreen, R300_TX_INVALTAGS, 1));
-   OUT_BATCH(R300_TX_FLUSH);
+   OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
    END_BATCH();
    end_3d(radeon);
 }