Mesa (master): r300-gallium: Move all unsorted state into invariant state.
Corbin Simpson
csimpson at kemper.freedesktop.org
Tue Mar 17 20:14:27 UTC 2009
Module: Mesa
Branch: master
Commit: 5deefb7ea5a3c545a6b275d50753d1f232c905d5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5deefb7ea5a3c545a6b275d50753d1f232c905d5
Author: Corbin Simpson <MostAwesomeDude at gmail.com>
Date: Tue Mar 17 13:11:55 2009 -0700
r300-gallium: Move all unsorted state into invariant state.
Gotta just slowly whittle this down.
---
src/gallium/drivers/r300/r300_state_invariant.c | 124 +++++++++++++++++++++++
src/gallium/drivers/r300/r300_surface.c | 123 ----------------------
2 files changed, 124 insertions(+), 123 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_state_invariant.c b/src/gallium/drivers/r300/r300_state_invariant.c
index 5646d22..e584bfb 100644
--- a/src/gallium/drivers/r300/r300_state_invariant.c
+++ b/src/gallium/drivers/r300/r300_state_invariant.c
@@ -76,4 +76,128 @@ void r300_emit_invariant_state(struct r300_context* r300)
}
END_CS;
+
+ /* XXX unsorted stuff from surface_fill */
+ BEGIN_CS(99 + (caps->has_tcl ? 28 : 0));
+ /* Flush PVS. */
+ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
+
+ OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
+ R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
+ R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
+ R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
+ /* Max and min vertex index clamp. */
+ OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
+ OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
+ /* XXX endian */
+ if (caps->has_tcl) {
+ OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
+ OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
+ R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
+ OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(1.0);
+ OUT_CS_32F(1.0);
+ } else {
+ OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP |
+ R300_VAP_TCL_BYPASS);
+ }
+ /* XXX magic number not in r300_reg */
+ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
+ /* XXX point tex stuffing */
+ OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
+ OUT_CS_32F(0.0);
+ OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
+ OUT_CS_32F(1.0);
+ OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
+ (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
+ /* XXX this big chunk should be refactored into rs_state */
+ OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
+ OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
+ OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
+ OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
+ OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
+ OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
+ OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
+ OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
+ OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
+ OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
+ OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
+ OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
+ OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
+ OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
+ OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
+ OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
+ OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
+ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
+ OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
+ OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
+ OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
+ OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
+ if (caps->has_tcl) {
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
+ ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
+ R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
+ } else {
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
+ (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
+ ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
+ R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
+ }
+ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+ (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE0_SHIFT) |
+ (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE1_SHIFT));
+ OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
+ OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
+ OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
+ /* Vertex size. */
+ OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
+ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
+ OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
+ OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
+ OUT_CS_REG(R300_TX_ENABLE, 0x0);
+
+ /* XXX */
+ OUT_CS_REG(R300_SC_CLIP_RULE, 0xaaaa);
+
+ OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
+ OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
+ OUT_CS(R300_US_OUT_FMT_UNUSED);
+ OUT_CS(R300_US_OUT_FMT_UNUSED);
+ OUT_CS(R300_US_OUT_FMT_UNUSED);
+ OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
+ /* XXX these magic numbers should be explained when
+ * this becomes a cached state object */
+ if (caps->has_tcl) {
+ OUT_CS_REG(R300_VAP_CNTL, 0xA |
+ (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
+ (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
+ OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
+ OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
+ OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
+ /* XXX translate these back into normal instructions */
+ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
+ OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
+ OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8);
+ OUT_CS(0x00F00203);
+ OUT_CS(0x00D10001);
+ OUT_CS(0x01248001);
+ OUT_CS(0x00000000);
+ OUT_CS(0x00F02203);
+ OUT_CS(0x00D10021);
+ OUT_CS(0x01248021);
+ OUT_CS(0x00000000);
+ } else {
+ OUT_CS_REG(R300_VAP_CNTL, 0xA |
+ (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+ (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
+ (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
+ }
+ END_CS;
}
diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c
index f825fad..2cc0677 100644
--- a/src/gallium/drivers/r300/r300_surface.c
+++ b/src/gallium/drivers/r300/r300_surface.c
@@ -67,129 +67,6 @@ static void r300_surface_fill(struct pipe_context* pipe,
r300_emit_rs_block_state(r300, &r300_rs_block_clear_state);
}
- BEGIN_CS(99 + (caps->has_tcl ? 28 : 0));
- /* Flush PVS. */
- OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
-
- OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
- R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
- R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
- R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
- /* Max and min vertex index clamp. */
- OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
- OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
- /* XXX endian */
- if (caps->has_tcl) {
- OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
- OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
- R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
- OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
- OUT_CS_32F(1.0);
- OUT_CS_32F(1.0);
- OUT_CS_32F(1.0);
- OUT_CS_32F(1.0);
- } else {
- OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP |
- R300_VAP_TCL_BYPASS);
- }
- /* XXX magic number not in r300_reg */
- OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
- /* XXX point tex stuffing */
- OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
- OUT_CS_32F(0.0);
- OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
- OUT_CS_32F(1.0);
- OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
- (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
- /* XXX this big chunk should be refactored into rs_state */
- OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
- OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
- OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
- OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
- OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
- OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
- OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
- OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
- OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
- OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
- OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
- OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
- OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
- OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
- OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
- OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
- OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
- OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
- OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
- OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
- OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
- OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
- OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
- OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
- OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
- if (caps->has_tcl) {
- OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
- (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
- ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
- R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
- } else {
- OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
- (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
- ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
- R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
- }
- OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
- (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE0_SHIFT) |
- (R300_VAP_SWIZZLE_XYZW << R300_SWIZZLE1_SHIFT));
- OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
- OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
- OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
- /* Vertex size. */
- OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
- OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
- OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
- OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
- OUT_CS_REG(R300_TX_ENABLE, 0x0);
-
- /* XXX */
- OUT_CS_REG(R300_SC_CLIP_RULE, 0xaaaa);
-
- OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
- OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
- OUT_CS(R300_US_OUT_FMT_UNUSED);
- OUT_CS(R300_US_OUT_FMT_UNUSED);
- OUT_CS(R300_US_OUT_FMT_UNUSED);
- OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
- /* XXX these magic numbers should be explained when
- * this becomes a cached state object */
- if (caps->has_tcl) {
- OUT_CS_REG(R300_VAP_CNTL, 0xA |
- (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
- (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
- OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
- OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
- OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
- /* XXX translate these back into normal instructions */
- OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
- OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
- OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 8);
- OUT_CS(0x00F00203);
- OUT_CS(0x00D10001);
- OUT_CS(0x01248001);
- OUT_CS(0x00000000);
- OUT_CS(0x00F02203);
- OUT_CS(0x00D10021);
- OUT_CS(0x01248021);
- OUT_CS(0x00000000);
- } else {
- OUT_CS_REG(R300_VAP_CNTL, 0xA |
- (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
- (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
- (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
- }
- END_CS;
-
BEGIN_CS(36);
/* Viewport setup */
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