Mesa (radeon-rewrite): r300: set proper texture row alignment for IGP chips

[Alex Deucher]

Module: Mesa
Branch: radeon-rewrite
Commit: 0b22615c2c860968a027c04519e25864ae69f6cd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b22615c2c860968a027c04519e25864ae69f6cd

Author: Maciej Cencora <m.cencora at gmail.com>
Date:   Sat May  2 17:27:03 2009 +0200

r300: set proper texture row alignment for IGP chips

Looks like r400 based IGP chips require 64 byte alignment

---

 src/mesa/drivers/dri/r300/r300_context.c           |    5 +++++
 .../drivers/dri/radeon/radeon_common_context.c     |    2 ++
 .../drivers/dri/radeon/radeon_common_context.h     |    1 +
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |   11 ++++++-----
 4 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index 4d1f10b..70c7730 100644
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -412,6 +412,11 @@ GLboolean r300CreateContext(const __GLcontextModes * glVisual,
 	if (r300->radeon.radeonScreen->kernel_mm)
 	  driInitExtensions(ctx, mm_extensions, GL_FALSE);
 
+	if (screen->chip_family == CHIP_FAMILY_RS600 ||	screen->chip_family == CHIP_FAMILY_RS690 ||
+		screen->chip_family == CHIP_FAMILY_RS740) {
+		r300->radeon.texture_row_align = 64;
+	}
+
 	r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache,
 						     "def_max_anisotropy");
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index ba74c97..3e71362 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -177,6 +177,8 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
                 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
 	        DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
+	radeon->texture_row_align = 32;
+
 	return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index d32e5af..181688c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -421,6 +421,7 @@ struct radeon_context {
     */
    int                   texture_depth;
    float                 initialMaxAnisotropy;
+   uint32_t              texture_row_align;
 
   struct radeon_dma dma;
   struct radeon_hw_state hw;
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
index 34d6261..51538e3 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
@@ -86,10 +86,11 @@ static int radeon_compressed_num_bytes(GLuint mesaFormat)
  * \param curOffset points to the offset at which the image is to be stored
  * and is updated by this function according to the size of the image.
  */
-static void compute_tex_image_offset(radeon_mipmap_tree *mt,
+static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree *mt,
 	GLuint face, GLuint level, GLuint* curOffset)
 {
 	radeon_mipmap_level *lvl = &mt->levels[level];
+	uint32_t row_align = rmesa->texture_row_align - 1;
 
 	/* Find image size in bytes */
 	if (mt->compressed) {
@@ -107,7 +108,7 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
 		lvl->rowstride = (lvl->width * mt->bpp * 2 + 31) & ~31;
 		lvl->size = lvl->rowstride * ((lvl->height + 1) / 2) * lvl->depth;
 	} else {
-		lvl->rowstride = (lvl->width * mt->bpp + 31) & ~31;
+		lvl->rowstride = (lvl->width * mt->bpp + row_align) & ~row_align;
 		lvl->size = lvl->rowstride * lvl->height * lvl->depth;
 	}
 	assert(lvl->size > 0);
@@ -131,7 +132,7 @@ static GLuint minify(GLuint size, GLuint levels)
 	return size;
 }
 
-static void calculate_miptree_layout(radeon_mipmap_tree *mt)
+static void calculate_miptree_layout(radeonContextPtr rmesa, radeon_mipmap_tree *mt)
 {
 	GLuint curOffset;
 	GLuint numLevels;
@@ -149,7 +150,7 @@ static void calculate_miptree_layout(radeon_mipmap_tree *mt)
 		mt->levels[i].depth = minify(mt->depth0, i);
 
 		for(face = 0; face < mt->faces; face++)
-			compute_tex_image_offset(mt, face, i, &curOffset);
+			compute_tex_image_offset(rmesa, mt, face, i, &curOffset);
 	}
 
 	/* Note the required size in memory */
@@ -181,7 +182,7 @@ radeon_mipmap_tree* radeon_miptree_create(radeonContextPtr rmesa, radeonTexObj *
 	mt->tilebits = tilebits;
 	mt->compressed = compressed;
 
-	calculate_miptree_layout(mt);
+	calculate_miptree_layout(rmesa, mt);
 
 	mt->bo = radeon_bo_open(rmesa->radeonScreen->bom,
                             0, mt->totalsize, 1024,