Mesa (master): i965: Fix varying payload reg assignment for the non-GLSL-instructions path.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: dc657f3929fbe03275b3fae4ef84f02e74b51114
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc657f3929fbe03275b3fae4ef84f02e74b51114

Author: Eric Anholt <eric at anholt.net>
Date:   Thu May 14 10:56:32 2009 -0700

i965: Fix varying payload reg assignment for the non-GLSL-instructions path.

I don't have a testcase for this, but it seems clearly wrong.

---

 src/mesa/drivers/dri/i965/brw_wm_pass2.c |   18 ++++++++++--------
 1 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 08cac73..6faea01 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,7 +69,6 @@ static void prealloc_reg(struct brw_wm_compile *c,
  */
 static void init_registers( struct brw_wm_compile *c )
 {
-   struct brw_context *brw = c->func.brw;
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -85,15 +84,18 @@ static void init_registers( struct brw_wm_compile *c )
 
    for (j = 0; j < FRAG_ATTRIB_MAX; j++) {
       if (c->key.vp_outputs_written & (1<<j)) {
-	 /* index for vs output and ps input are not the same 
-	    in shader varying */
-	 GLuint index;
-	 if (j > FRAG_ATTRIB_VAR0)
-	     index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	 int fp_index;
+
+	 if (j >= VERT_RESULT_VAR0)
+	    fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	 else if (j <= VERT_RESULT_TEX7)
+	    fp_index = j;
 	 else
-	     index = j;
+	    fp_index = -1;
+
 	 nr_interp_regs++;
-	 prealloc_reg(c, &c->payload.input_interp[index], i++);
+	 if (fp_index >= 0)
+	    prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
       }
    }