Mesa (radeon-rewrite): radeon: emit scissor when using cs submission style.

Jerome Glisse glisse at kemper.freedesktop.org
Wed May 27 07:36:59 UTC 2009


Module: Mesa
Branch: radeon-rewrite
Commit: 6141c9ba71df68c44fb4f8c9409f23b557009ca0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6141c9ba71df68c44fb4f8c9409f23b557009ca0

Author: Jerome Glisse <glisse at freedesktop.org>
Date:   Wed May 27 09:36:07 2009 +0200

radeon: emit scissor when using cs submission style.

---

 src/mesa/drivers/dri/radeon/radeon_ioctl.c |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index caa0c4a..8f8878e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -113,6 +113,31 @@ void radeonSetUpAtomList( r100ContextPtr rmesa )
    insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt);
 }
 
+void radeonEmitScissor(r100ContextPtr rmesa)
+{
+    BATCH_LOCALS(&rmesa->radeon);
+    if (!rmesa->radeon.radeonScreen->kernel_mm) {
+       return;
+    }
+    if (rmesa->radeon.state.scissor.enabled) {
+        BEGIN_BATCH(6);
+        OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
+        OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE);
+        OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
+        OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
+                  rmesa->radeon.state.scissor.rect.x1);
+        OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
+        OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) |
+                  (rmesa->radeon.state.scissor.rect.x2 - 1));
+        END_BATCH();
+    } else {
+        BEGIN_BATCH(2);
+        OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0));
+        OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE);
+        END_BATCH();
+    }
+}
+
 /* Fire a section of the retained (indexed_verts) buffer as a regular
  * primtive.
  */
@@ -126,6 +151,7 @@ extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
    assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
 
    radeonEmitState(&rmesa->radeon);
+   radeonEmitScissor(rmesa);
 
 #if RADEON_OLD_PACKETS
    BEGIN_BATCH(8);
@@ -180,6 +206,8 @@ void radeonFlushElts( GLcontext *ctx )
    assert( rmesa->radeon.dma.flush == radeonFlushElts );
    rmesa->radeon.dma.flush = NULL;
 
+   radeonEmitScissor(rmesa);
+
    nr = rmesa->tcl.elt_used;
 
 #if RADEON_OLD_PACKETS




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