Mesa (master): r600: rework DB render setup
Alex Deucher
agd5f at kemper.freedesktop.org
Mon Nov 9 17:25:09 UTC 2009
Module: Mesa
Branch: master
Commit: 66d6f9e860143c3d705f1d78c324159cadd258cc
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66d6f9e860143c3d705f1d78c324159cadd258cc
Author: Alex Deucher <alexdeucher at gmail.com>
Date: Mon Nov 9 12:20:47 2009 -0500
r600: rework DB render setup
- consolidate DB render setup
- only enable perfect ZPASS counts and cull disable
when OQ is active
- enable early Z
---
src/mesa/drivers/dri/r600/r700_fragprog.c | 27 ++--------
src/mesa/drivers/dri/r600/r700_render.c | 4 +-
src/mesa/drivers/dri/r600/r700_state.c | 82 +++++++++++++++++++++++------
src/mesa/drivers/dri/r600/r700_state.h | 2 +-
4 files changed, 73 insertions(+), 42 deletions(-)
diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c
index 0f549ea..ccafd43 100644
--- a/src/mesa/drivers/dri/r600/r700_fragprog.c
+++ b/src/mesa/drivers/dri/r600/r700_fragprog.c
@@ -393,26 +393,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
EXPORT_MODE_shift, EXPORT_MODE_mask);
- R600_STATECHANGE(context, db);
-
- if(fp->r700Shader.killIsUsed)
- {
- SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
- }
- else
- {
- CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
- }
-
- if(fp->r700Shader.depthIsExported)
- {
- SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
- }
- else
- {
- CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
- }
-
// emit ps input map
unBit = 1 << FRAG_ATTRIB_WPOS;
if(mesa_fp->Base.InputsRead & unBit)
@@ -479,9 +459,12 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
}
}
- R600_STATECHANGE(context, cb);
exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
- r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
+ if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1))
+ {
+ R600_STATECHANGE(context, cb);
+ r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
+ }
/* sent out shader constants. */
paramList = fp->mesa_program.Base.Parameters;
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index c345b9d..47f89c9 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -59,9 +59,7 @@
void r700WaitForIdle(context_t *context);
void r700WaitForIdleClean(context_t *context);
-GLboolean r700SendTextureState(context_t *context);
static unsigned int r700PrimitiveType(int prim);
-void r600UpdateTextureState(GLcontext * ctx);
GLboolean r700SyncSurf(context_t *context,
struct radeon_bo *pbo,
uint32_t read_domain,
@@ -891,7 +889,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx,
r700SetScissor(context);
r700SetupVertexProgram(ctx);
r700SetupFragmentProgram(ctx);
- r600UpdateTextureState(ctx);
+ r700UpdateShaderStates(ctx);
GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims)
+ context->radeon.cmdbuf.cs->cdw;
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index b95fc87..41000dc 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -54,7 +54,7 @@
#include "r700_fragprog.h"
#include "r700_vertprog.h"
-
+void r600UpdateTextureState(GLcontext * ctx);
static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
static void r700UpdatePolygonMode(GLcontext * ctx);
static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
@@ -191,6 +191,70 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-----------
context->radeon.NewGLState |= new_state;
}
+static void r700SetDBRenderState(GLcontext * ctx)
+{
+ context_t *context = R700_CONTEXT(ctx);
+ R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+ struct r700_fragment_program *fp = (struct r700_fragment_program *)
+ (ctx->FragmentProgram._Current);
+
+ R600_STATECHANGE(context, db);
+
+ SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
+ SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
+ /* XXX not sure if this is required */
+ if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+ SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
+ /* XXX need to enable htile for hiz/s */
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
+ SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
+
+ if (context->radeon.query.current)
+ {
+ SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
+ if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+ {
+ SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
+ }
+ }
+ else
+ {
+ CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
+ if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+ {
+ CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
+ }
+ }
+
+ if (fp)
+ {
+ if (fp->r700Shader.killIsUsed)
+ {
+ SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
+ }
+ else
+ {
+ CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
+ }
+
+ if (fp->r700Shader.depthIsExported)
+ {
+ SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
+ }
+ else
+ {
+ CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
+ }
+ }
+}
+
+void r700UpdateShaderStates(GLcontext * ctx)
+{
+ r700SetDBRenderState(ctx);
+ r600UpdateTextureState(ctx);
+}
+
static void r700SetDepthState(GLcontext * ctx)
{
context_t *context = R700_CONTEXT(ctx);
@@ -1672,24 +1736,10 @@ void r700InitState(GLcontext * ctx) //-------------------
r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
r700DepthMask(ctx, ctx->Depth.Mask);
r700DepthFunc(ctx, ctx->Depth.Func);
- SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
-
r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
-
- r700->DB_RENDER_CONTROL.u32All = 0;
SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
- r700->DB_RENDER_OVERRIDE.u32All = 0;
- if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
- SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
- SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
- SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
- if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
- {
- CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
- }
+ r700SetDBRenderState(ctx);
r700->DB_ALPHA_TO_MASK.u32All = 0;
SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h
index 209189d..60c6a7f 100644
--- a/src/mesa/drivers/dri/r600/r700_state.h
+++ b/src/mesa/drivers/dri/r600/r700_state.h
@@ -35,7 +35,7 @@
extern void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state);
extern void r700UpdateShaders (GLcontext * ctx);
-extern void r700UpdateShaders2(GLcontext * ctx);
+extern void r700UpdateShaderStates(GLcontext * ctx);
extern void r700UpdateViewportOffset(GLcontext * ctx);
More information about the mesa-commit
mailing list