Mesa (mesa_7_5_branch): intel: Align cubemap texture height to its padding requirements.

[Eric Anholt]

Module: Mesa
Branch: mesa_7_5_branch
Commit: a9504edee344936ef496341174d4c2d76ee0c44d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9504edee344936ef496341174d4c2d76ee0c44d

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Aug 18 18:48:54 2009 -0700

intel: Align cubemap texture height to its padding requirements.
(cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d)
(cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)

---

 src/mesa/drivers/dri/i965/brw_tex_layout.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 51a617f..3ab27c2 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -119,6 +119,16 @@ GLboolean brw_miptree_layout( struct intel_context *intel, struct intel_mipmap_t
     }
 
       }
+      /* The 965's sampler lays cachelines out according to how accesses
+       * in the texture surfaces run, so they may be "vertical" through
+       * memory.  As a result, the docs say in Surface Padding Requirements:
+       * Sampling Engine Surfaces that two extra rows of padding are required.
+       * We don't know of similar requirements for pre-965, but given that
+       * those docs are silent on padding requirements in general, let's play
+       * it safe.
+       */
+      if (mt->target == GL_TEXTURE_CUBE_MAP)
+	 mt->total_height += 2;
       break;
    }