Mesa (master): i965: Use MI_FLUSH_DW for blt ring flush on sandybridge
Zhenyu Wang
zhen at kemper.freedesktop.org
Thu Dec 23 09:30:25 UTC 2010
Module: Mesa
Branch: master
Commit: 845d651cf686ba885dffd9e05df971fa68c3431a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=845d651cf686ba885dffd9e05df971fa68c3431a
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Thu Dec 23 15:06:33 2010 +0800
i965: Use MI_FLUSH_DW for blt ring flush on sandybridge
Old MI_FLUSH command is deprecated on sandybridge blt.
---
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 7 +++++--
src/mesa/drivers/dri/intel/intel_reg.h | 2 ++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 20574ab..67ce8a4 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -271,8 +271,11 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
if (intel->gen >= 6) {
if (intel->batch->is_blit) {
- BEGIN_BATCH_BLT(1);
- OUT_BATCH(MI_FLUSH);
+ BEGIN_BATCH_BLT(4);
+ OUT_BATCH(MI_FLUSH_DW);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(8);
diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index 955b100..5258699 100644
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -37,6 +37,8 @@
#define FLUSH_MAP_CACHE (1 << 0)
#define INHIBIT_FLUSH_RENDER_CACHE (1 << 2)
+#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2)
+
/* Stalls command execution waiting for the given events to have occurred. */
#define MI_WAIT_FOR_EVENT (CMD_MI | (0x3 << 23))
#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
More information about the mesa-commit
mailing list