Mesa (glsl2): glsl2: Add a pass to break ir_binop_div to _mul and _rcp.

[Eric Anholt]

Module: Mesa
Branch: glsl2
Commit: 9a0e421983edc31371440c08687fa2bb2207924d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a0e421983edc31371440c08687fa2bb2207924d

Author: Eric Anholt <eric at anholt.net>
Date:   Fri Jul  2 11:27:06 2010 -0700

glsl2: Add a pass to break ir_binop_div to _mul and _rcp.

This results in constant folding of a constant divisor.

---

 src/glsl/Makefile              |    1 +
 src/glsl/ir_div_to_mul_rcp.cpp |   77 ++++++++++++++++++++++++++++++++++++++++
 src/glsl/ir_optimization.h     |    1 +
 src/mesa/shader/ir_to_mesa.cpp |    5 +--
 4 files changed, 81 insertions(+), 3 deletions(-)

diff --git a/src/glsl/Makefile b/src/glsl/Makefile
index a709bf7..30ba475 100644
--- a/src/glsl/Makefile
+++ b/src/glsl/Makefile
@@ -33,6 +33,7 @@ CXX_SOURCES = \
 	ir.cpp \
 	ir_dead_code.cpp \
 	ir_dead_code_local.cpp \
+	ir_div_to_mul_rcp.cpp \
 	ir_expression_flattening.cpp \
 	ir_function_can_inline.cpp \
 	ir_function.cpp \
diff --git a/src/glsl/ir_div_to_mul_rcp.cpp b/src/glsl/ir_div_to_mul_rcp.cpp
new file mode 100644
index 0000000..ce84add
--- /dev/null
+++ b/src/glsl/ir_div_to_mul_rcp.cpp
@@ -0,0 +1,77 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file ir_div_to_mul_rcp.cpp
+ *
+ * Breaks an ir_unop_div expression down to op0 * (rcp(op1)).
+ *
+ * Many GPUs don't have a divide instruction (945 and 965 included),
+ * but they do have an RCP instruction to compute an approximate
+ * reciprocal.  By breaking the operation down, constant reciprocals
+ * can get constant folded.
+ */
+
+#include "ir.h"
+
+class ir_div_to_mul_rcp_visitor : public ir_hierarchical_visitor {
+public:
+   ir_div_to_mul_rcp_visitor()
+   {
+      this->made_progress = false;
+   }
+
+   ir_visitor_status visit_leave(ir_expression *);
+
+   bool made_progress;
+};
+
+bool
+do_div_to_mul_rcp(exec_list *instructions)
+{
+   ir_div_to_mul_rcp_visitor v;
+
+   visit_list_elements(&v, instructions);
+   return v.made_progress;
+}
+
+ir_visitor_status
+ir_div_to_mul_rcp_visitor::visit_leave(ir_expression *ir)
+{
+   if (ir->operation != ir_binop_div)
+      return visit_continue;
+
+   /* New expression for the 1.0 / op1 */
+   ir_rvalue *expr;
+   expr = new(ir) ir_expression(ir_unop_rcp,
+				ir->operands[1]->type,
+				ir->operands[1],
+				NULL);
+
+   /* op0 / op1 -> op0 * (1.0 / op1) */
+   ir->operation = ir_binop_mul;
+   ir->operands[1] = expr;
+   this->made_progress = true;
+
+   return visit_continue;
+}
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 1a8b740..6d02e59 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -37,6 +37,7 @@ bool do_dead_code(struct _mesa_glsl_parse_state *state,
 bool do_dead_code_local(exec_list *instructions);
 bool do_dead_code_unlinked(struct _mesa_glsl_parse_state *state,
 			   exec_list *instructions);
+bool do_div_to_mul_rcp(exec_list *instructions);
 bool do_function_inlining(exec_list *instructions);
 bool do_if_simplification(exec_list *instructions);
 bool do_mod_to_fract(exec_list *instructions);
diff --git a/src/mesa/shader/ir_to_mesa.cpp b/src/mesa/shader/ir_to_mesa.cpp
index 7c7e368..d5664e7 100644
--- a/src/mesa/shader/ir_to_mesa.cpp
+++ b/src/mesa/shader/ir_to_mesa.cpp
@@ -691,9 +691,7 @@ ir_to_mesa_visitor::visit(ir_expression *ir)
       }
       break;
    case ir_binop_div:
-      ir_to_mesa_emit_scalar_op1(ir, OPCODE_RCP, result_dst, op[1]);
-      ir_to_mesa_emit_op2(ir, OPCODE_MUL, result_dst, op[0], result_src);
-      break;
+      assert(!"not reached: should be handled by ir_div_to_mul_rcp");
    case ir_binop_mod:
       assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
       break;
@@ -1729,6 +1727,7 @@ _mesa_glsl_compile_shader(GLcontext *ctx, struct gl_shader *shader)
 
    /* Lowering */
    do_mod_to_fract(shader->ir);
+   do_div_to_mul_rcp(shader->ir);
 
    /* Optimization passes */
    if (!state->error && !shader->ir->is_empty()) {