Mesa (master): r300g: reorder and cleanup register writes everywhere

Marek Olšák mareko at kemper.freedesktop.org
Wed Jun 23 21:11:07 PDT 2010


Module: Mesa
Branch: master
Commit: a2f14153cc2bcf0b2364e035dc788d65ea0fcd35
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2f14153cc2bcf0b2364e035dc788d65ea0fcd35

Author: Marek Olšák <maraeo at gmail.com>
Date:   Thu Jun 24 03:52:45 2010 +0200

r300g: reorder and cleanup register writes everywhere

---

 src/gallium/drivers/r300/r300_context.c         |   25 +++++---
 src/gallium/drivers/r300/r300_emit.c            |   50 ++++++++++++++--
 src/gallium/drivers/r300/r300_fs.c              |    5 ++
 src/gallium/drivers/r300/r300_state.c           |    8 ++-
 src/gallium/drivers/r300/r300_state_invariant.c |   71 +++-------------------
 5 files changed, 79 insertions(+), 80 deletions(-)

diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index 16a75aa..b35c91a 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -117,27 +117,34 @@ static void r300_setup_atoms(struct r300_context* r300)
      * Some atoms never change size, others change every emit - those have
      * the size of 0 here. */
     make_empty_list(&r300->atom_list);
+    /* XXX unsorted. */
     R300_INIT_ATOM(invariant_state, 71);
+    /* RB3D (unpipelined), ZB (unpipelined), US, SC. */
+    R300_INIT_ATOM(fb_state, 0);
     R300_INIT_ATOM(ztop_state, 2);
-    R300_INIT_ATOM(query_start, 4);
+    R300_INIT_ATOM(dsa_state, is_r500 ? 8 : 6);
     R300_INIT_ATOM(blend_state, 8);
     R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
-    R300_INIT_ATOM(clip_state, has_tcl ? 5 + (6 * 4) : 2);
-    R300_INIT_ATOM(dsa_state, is_r500 ? 8 : 6);
-    R300_INIT_ATOM(fb_state, 0);
-    R300_INIT_ATOM(rs_state, 0);
     R300_INIT_ATOM(scissor_state, 3);
+    /* VAP. */
     R300_INIT_ATOM(viewport_state, 9);
-    R300_INIT_ATOM(rs_block_state, 0);
-    R300_INIT_ATOM(vertex_stream_state, 0);
     R300_INIT_ATOM(pvs_flush, 2);
+    R300_INIT_ATOM(vertex_stream_state, 0);
     R300_INIT_ATOM(vs_state, 0);
     R300_INIT_ATOM(vs_constants, 0);
-    R300_INIT_ATOM(texture_cache_inval, 2);
-    R300_INIT_ATOM(textures_state, 0);
+    R300_INIT_ATOM(clip_state, has_tcl ? 5 + (6 * 4) : 2);
+    /* VAP, RS, GA, GB. */
+    R300_INIT_ATOM(rs_block_state, 0);
+    R300_INIT_ATOM(rs_state, 0);
+    /* US. */
     R300_INIT_ATOM(fs, 0);
     R300_INIT_ATOM(fs_rc_constant_state, 0);
     R300_INIT_ATOM(fs_constants, 0);
+    /* TX. */
+    R300_INIT_ATOM(texture_cache_inval, 2);
+    R300_INIT_ATOM(textures_state, 0);
+    /* ZB (unpipelined), SU. */
+    R300_INIT_ATOM(query_start, 4);
 
     /* Replace emission functions for r500. */
     if (r300->screen->caps.is_r500) {
diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index e2c40d8..a5fa06a 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -303,6 +303,13 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
      * by incomplete rendering. */
     OUT_CS_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 
+    /* XXX unpipelined regs
+    rb3d_aaresolve_ctl
+    rb3d_aaresolve_offset
+    rb3d_aaresolve_pitch
+    gb_aa_config
+    */
+
     /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
      * what we usually want. */
     if (r300->screen->caps.is_r500) {
@@ -321,24 +328,42 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
 
         OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
         OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
-
-        OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), surf->format);
-    }
-    for (; i < 4; i++) {
-        OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
     }
 
     /* Set up a zbuffer. */
     if (fb->zsbuf) {
         surf = r300_surface(fb->zsbuf);
 
+        OUT_CS_REG(R300_ZB_FORMAT, surf->format);
+        OUT_CS_REG(R300_ZB_BW_CNTL, 0);
+
         OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
         OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain, 0);
 
-        OUT_CS_REG(R300_ZB_FORMAT, surf->format);
-
         OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
         OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain, 0);
+
+        OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0);
+
+        /* HiZ RAM. */
+        if (r300->screen->caps.has_hiz) {
+            OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
+            OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
+        }
+
+        /* Z Mask RAM. (compressed zbuffer) */
+        OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
+        OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
+    }
+
+    /* Colorbuffer format in the US block.
+     * (must be written after unpipelined regs) */
+    OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
+    for (i = 0; i < fb->nr_cbufs; i++) {
+        OUT_CS(r300_surface(fb->cbufs[i])->format);
+    }
+    for (; i < 4; i++) {
+        OUT_CS(R300_US_OUT_FMT_UNUSED);
     }
     END_CS;
 }
@@ -813,6 +838,17 @@ void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
     CS_LOCALS(r300);
 
     BEGIN_CS(size);
+    /* Amount of time to wait for vertex fetches in PVS */
+    OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
+
+    OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
+    OUT_CS_32F(1.0);
+    OUT_CS_32F(1.0);
+    OUT_CS_32F(1.0);
+    OUT_CS_32F(1.0);
+
+    OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
+
     /* R300_VAP_PVS_CODE_CNTL_0
      * R300_VAP_PVS_CONST_CNTL
      * R300_VAP_PVS_CODE_CNTL_1
diff --git a/src/gallium/drivers/r300/r300_fs.c b/src/gallium/drivers/r300/r300_fs.c
index e585394..424f831 100644
--- a/src/gallium/drivers/r300/r300_fs.c
+++ b/src/gallium/drivers/r300/r300_fs.c
@@ -288,11 +288,16 @@ static void r300_emit_fs_code_to_buffer(
         struct r300_fragment_program_code *code = &generic_code->code.r300;
 
         shader->cb_code_size = 19 +
+                               (r300->screen->caps.is_r400 ? 2 : 0) +
                                code->alu.length * 4 +
                                (code->tex.length ? (1 + code->tex.length) : 0) +
                                imm_count * 5;
 
         NEW_CB(shader->cb_code, shader->cb_code_size);
+
+        if (r300->screen->caps.is_r400)
+            OUT_CB_REG(R400_US_CODE_BANK, 0);
+
         OUT_CB_REG(R300_US_CONFIG, code->config);
         OUT_CB_REG(R300_US_PIXSIZE, code->pixsize);
         OUT_CB_REG(R300_US_CODE_OFFSET, code->code_offset);
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 927e936..247a590 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -702,8 +702,10 @@ static void
 
     memcpy(r300->fb_state.state, state, sizeof(struct pipe_framebuffer_state));
 
-    r300->fb_state.size = (10 * state->nr_cbufs) + (2 * (4 - state->nr_cbufs)) +
-                          (state->zsbuf ? 10 : 0) + 11;
+    r300->fb_state.size =
+            16 +
+            (8 * state->nr_cbufs) +
+            (state->zsbuf ? (r300->screen->caps.has_hiz ? 22 : 18) : 0);
 
     /* Polygon offset depends on the zbuffer bit depth. */
     if (state->zsbuf && r300->polygon_offset_enabled) {
@@ -1575,7 +1577,7 @@ static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
     if (r300->screen->caps.has_tcl) {
         r300->vs_state.dirty = TRUE;
         r300->vs_state.size =
-                vs->code.length + 9 +
+                vs->code.length + 18 +
                 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0);
 
         if (vs->externals_count) {
diff --git a/src/gallium/drivers/r300/r300_state_invariant.c b/src/gallium/drivers/r300/r300_state_invariant.c
index e67a0ae..bec6ea1 100644
--- a/src/gallium/drivers/r300/r300_state_invariant.c
+++ b/src/gallium/drivers/r300/r300_state_invariant.c
@@ -38,74 +38,23 @@ void r300_emit_invariant_state(struct r300_context* r300,
 {
     CS_LOCALS(r300);
 
-    BEGIN_CS(12 + (r300->screen->caps.has_tcl ? 2 : 0));
-
-    /*** Graphics Backend (GB) ***/
-    /* Source of fog depth */
-    OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
-
-    /*** Fog (FG) ***/
-    OUT_CS_REG(R300_FG_FOG_BLEND, 0x0);
-    OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x0);
-    OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x0);
-    OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x0);
-
-    /*** VAP ***/
-    /* Sign/normalize control */
-    OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
-    /* TCL-only stuff */
-    if (r300->screen->caps.has_tcl) {
-        /* Amount of time to wait for vertex fetches in PVS */
-        OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
-    }
-
-    END_CS;
-
-    /* XXX unsorted stuff from surface_fill */
-    BEGIN_CS(38 + (r300->screen->caps.has_tcl ? 7 : 0) +
-             (r300->screen->caps.is_rv350 ? 4 : 0) +
-             (r300->screen->caps.is_r400 ? 2 : 0));
-
-    if (r300->screen->caps.has_tcl) {
-        /*Flushing PVS is required before the VAP_GB registers can be changed*/
-        OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-        OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
-        OUT_CS_32F(1.0);
-        OUT_CS_32F(1.0);
-        OUT_CS_32F(1.0);
-        OUT_CS_32F(1.0);
-    }
-    /* XXX line tex stuffing */
-    OUT_CS_REG_SEQ(R300_GA_LINE_S0, 1);
-    OUT_CS_32F(0.0);
-    OUT_CS_REG_SEQ(R300_GA_LINE_S1, 1);
-    OUT_CS_32F(1.0);
-    OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
-        (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
-    /* XXX this big chunk should be refactored into rs_state */
-    OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
-    OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
-    OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
-    OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
-    OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
-    OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
-    OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
+    BEGIN_CS(20 + (r300->screen->caps.is_rv350 ? 4 : 0));
+
+    OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0);
+    OUT_CS_REG(R300_GB_SELECT, 0);
+    OUT_CS_REG(R300_FG_FOG_BLEND, 0);
+    OUT_CS_REG(R300_GA_ROUND_MODE, 1);
+    OUT_CS_REG(R300_GA_OFFSET, 0);
+    OUT_CS_REG(R300_SU_TEX_WRAP, 0);
     OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
-    OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
-    OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
+    OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0);
+    OUT_CS_REG(R300_SC_HYPERZ, 0x1C);
     OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
-    OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
 
     if (r300->screen->caps.is_rv350) {
         OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
         OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
     }
 
-    OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
-    OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
-    OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
-    OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
-    if (r300->screen->caps.is_r400)
-        OUT_CS_REG(R400_US_CODE_BANK, 0);
     END_CS;
 }



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