Mesa (master): i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 6e2330daa6d7872405485ffabfe613a7c053d890
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e2330daa6d7872405485ffabfe613a7c053d890

Author: Eric Anholt <eric at anholt.net>
Date:   Sun May 23 20:25:02 2010 -0700

i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.

---

 src/mesa/drivers/dri/i965/brw_misc_state.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 3b3cb5a..afe04c5 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -182,6 +182,13 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
 {
    struct intel_context *intel = &brw->intel;
 
+   if (intel->gen == 5) {
+      /* Need to flush before changing clip max threads for errata. */
+      BEGIN_BATCH(1);
+      OUT_BATCH(MI_FLUSH);
+      ADVANCE_BATCH();
+   }
+
    BEGIN_BATCH(7);
    OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
    OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);