Mesa (master): i965: Quit spamming gen6 DP read/ write send instructions with gen5 bits.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 4673f9433fb73febce796945e3883274636fbf62
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4673f9433fb73febce796945e3883274636fbf62

Author: Eric Anholt <eric at anholt.net>
Date:   Thu Apr 14 20:25:33 2011 -0700

i965: Quit spamming gen6 DP read/write send instructions with gen5 bits.

This was copy-and-paste from originally trying to get DP read/write
working reliably, and notably for other common messages (URB, sampler)
we weren't doing this.

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2d654e7..71485cd 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -499,9 +499,6 @@ static void brw_set_dp_write_message( struct brw_context *brw,
 
        /* We always use the render cache for write messages */
        insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
-	/* XXX really need below? */
-       insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_WRITE;
-       insn->bits2.send_gen5.end_of_thread = end_of_thread;
    } else if (intel->gen == 5) {
        insn->bits3.dp_write_gen5.binding_table_index = binding_table_index;
        insn->bits3.dp_write_gen5.msg_control = msg_control;
@@ -558,9 +555,6 @@ brw_set_dp_read_message(struct brw_context *brw,
        insn->bits3.dp_render_cache.msg_length = msg_length;
        insn->bits3.dp_render_cache.end_of_thread = 0;
        insn->header.destreg__conditionalmod = target_function;
-	/* XXX really need below? */
-       insn->bits2.send_gen5.sfid = target_function;
-       insn->bits2.send_gen5.end_of_thread = 0;
    } else if (intel->gen == 5) {
        insn->bits3.dp_read_gen5.binding_table_index = binding_table_index;
        insn->bits3.dp_read_gen5.msg_control = msg_control;