Mesa (master): i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.

Kenneth Graunke kwg at kemper.freedesktop.org
Mon Apr 18 15:26:37 PDT 2011


Module: Mesa
Branch: master
Commit: ff5dd55e264d8f0282aa3ae3dc4f6ab26d98731d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff5dd55e264d8f0282aa3ae3dc4f6ab26d98731d

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Apr 14 14:37:46 2011 -0700

i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.

Most of the newer portions of the code use OUT_BATCH style.  I prefer
this style because it offers a clear distinction between a) hardware
messages/structures with a mandatory format, and b) data structures for
our own internal use that we can format however we want.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/brw_defines.h |   11 +++---
 src/mesa/drivers/dri/i965/brw_draw.c    |   53 ++++++++++++++++++-------------
 src/mesa/drivers/dri/i965/brw_structs.h |   19 -----------
 3 files changed, 37 insertions(+), 46 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3078504..effcb6c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -43,6 +43,12 @@
 #define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00
 #define PIPE_CONTROL_GTTWRITE_GLOBAL        0x01
 
+#define CMD_3D_PRIM                                 0x7b00 /* 3DPRIMITIVE */
+/* DW0 */
+# define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT            10
+# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15)
+# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 15)
+
 #define _3DPRIM_POINTLIST         0x01
 #define _3DPRIM_LINELIST          0x02
 #define _3DPRIM_LINESTRIP         0x03
@@ -65,9 +71,6 @@
 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x15
 
-#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0
-#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     1
-
 #define BRW_ANISORATIO_2     0 
 #define BRW_ANISORATIO_4     1 
 #define BRW_ANISORATIO_6     2 
@@ -1132,8 +1135,6 @@
 
 #define CMD_PIPE_CONTROL              0x7a00
 
-#define CMD_3D_PRIM                   0x7b00
-
 #define CMD_MI_FLUSH                  0x0200
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 63ae28f..2db70c5 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -129,30 +129,31 @@ static void brw_emit_prim(struct brw_context *brw,
 			  const struct _mesa_prim *prim,
 			  uint32_t hw_prim)
 {
-   struct brw_3d_primitive prim_packet;
    struct intel_context *intel = &brw->intel;
+   int verts_per_instance;
+   int vertex_access_type;
+   int start_vertex_location;
+   int base_vertex_location;
 
    DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode),
        prim->start, prim->count);
 
-   prim_packet.header.opcode = CMD_3D_PRIM;
-   prim_packet.header.length = sizeof(prim_packet)/4 - 2;
-   prim_packet.header.pad = 0;
-   prim_packet.header.topology = hw_prim;
-   prim_packet.header.indexed = prim->indexed;
-
-   prim_packet.verts_per_instance = trim(prim->mode, prim->count);
-   prim_packet.start_vert_location = prim->start;
-   if (prim->indexed)
-      prim_packet.start_vert_location += brw->ib.start_vertex_offset;
-   else
-      prim_packet.start_vert_location += brw->vb.start_vertex_bias;
-   prim_packet.instance_count = 1;
-   prim_packet.start_instance_location = 0;
-   prim_packet.base_vert_location = prim->basevertex;
-   if (prim->indexed)
-      prim_packet.base_vert_location += brw->vb.start_vertex_bias;
+   start_vertex_location = prim->start;
+   base_vertex_location = prim->basevertex;
+   if (prim->indexed) {
+      vertex_access_type = GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM;
+      start_vertex_location += brw->ib.start_vertex_offset;
+      base_vertex_location += brw->vb.start_vertex_bias;
+   } else {
+      vertex_access_type = GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL;
+      start_vertex_location += brw->vb.start_vertex_bias;
+   }
+
+   verts_per_instance = trim(prim->mode, prim->count);
 
+   /* If nothing to emit, just return. */
+   if (verts_per_instance == 0)
+      return;
 
    /* If we're set to always flush, do it before and after the primitive emit.
     * We want to catch both missed flushes that hurt instruction/state cache
@@ -162,10 +163,18 @@ static void brw_emit_prim(struct brw_context *brw,
    if (intel->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(intel);
    }
-   if (prim_packet.verts_per_instance) {
-      intel_batchbuffer_data(&brw->intel, &prim_packet,
-			      sizeof(prim_packet), false);
-   }
+
+   BEGIN_BATCH(6);
+   OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) |
+	     hw_prim << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT |
+	     vertex_access_type);
+   OUT_BATCH(verts_per_instance);
+   OUT_BATCH(start_vertex_location);
+   OUT_BATCH(1); // instance count
+   OUT_BATCH(0); // start instance location
+   OUT_BATCH(base_vertex_location);
+   ADVANCE_BATCH();
+
    if (intel->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(intel);
    }
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 6687a89..89b1ee4 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -80,25 +80,6 @@ struct brw_3d_control
    GLuint dword3;   
 };
 
-
-struct brw_3d_primitive
-{
-   struct
-   {
-      GLuint length:8; 
-      GLuint pad:2;
-      GLuint topology:5; 
-      GLuint indexed:1; 
-      GLuint opcode:16; 
-   } header;
-
-   GLuint verts_per_instance;  
-   GLuint start_vert_location;  
-   GLuint instance_count;  
-   GLuint start_instance_location;  
-   GLuint base_vert_location;  
-};
-
 /* These seem to be passed around as function args, so it works out
  * better to keep them as #defines:
  */



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