Mesa (master): i965/fs: Rudimentary support for non-floating point texture results.

Kenneth Graunke kwg at kemper.freedesktop.org
Tue Aug 23 11:18:40 PDT 2011


Module: Mesa
Branch: master
Commit: b6bdcf2a908889532ef6d5eb643791176dffcb9d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6bdcf2a908889532ef6d5eb643791176dffcb9d

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Aug 18 00:18:15 2011 -0700

i965/fs: Rudimentary support for non-floating point texture results.

Not all texturing operations return floating point data.  For example,
the resinfo message (textureSize or TXS) returns integer data.  In the
future, we'll also add integer texture support.

ir_texture's type field contains this information; use its base type to
appropriately type the destination register.  We want to keep it as a
four component vector, however, since SIMD8 samplers always have a
response length of 4.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>

---

 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 764351a..792799d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1075,7 +1075,7 @@ fs_visitor::visit(ir_texture *ir)
    /* Writemasking doesn't eliminate channels on SIMD8 texture
     * samples, so don't worry about them.
     */
-   fs_reg dst = fs_reg(this, glsl_type::vec4_type);
+   fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
 
    if (intel->gen >= 7) {
       inst = emit_texture_gen7(ir, dst, coordinate, sampler);



More information about the mesa-commit mailing list