Mesa (master): radeon: Fix flushing before writing a teximage's BO when !t- >bo.
Eric Anholt
anholt at kemper.freedesktop.org
Wed Aug 24 17:44:57 UTC 2011
Module: Mesa
Branch: master
Commit: 4990e7e9fb6d64f5e4c23915767e5cea32c02965
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4990e7e9fb6d64f5e4c23915767e5cea32c02965
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 3 18:29:36 2011 -0700
radeon: Fix flushing before writing a teximage's BO when !t->bo.
Before, if we ended up here without a BO for our image, but did choose
a miptree that had active rendering in the command buffer, our
teximage data would jump ahead of the rendering using the old texture
contents.
This showed up as breakage in gen-teximage and friends in the
following commit.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
---
src/mesa/drivers/dri/radeon/radeon_texture.c | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
index ce0df32..ad7e4c1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -787,18 +787,6 @@ static void radeon_teximage(
radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
"%s %dd: texObj %p, texImage %p, face %d, level %d\n",
__func__, dims, texObj, texImage, face, level);
- {
- struct radeon_bo *bo;
- bo = !image->mt ? image->bo : image->mt->bo;
- if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) {
- radeon_print(RADEON_TEXTURE, RADEON_VERBOSE,
- "%s Calling teximage for texture that is "
- "queued for GPU processing.\n",
- __func__);
- radeon_firevertices(rmesa);
- }
- }
-
t->validated = GL_FALSE;
@@ -820,6 +808,18 @@ static void radeon_teximage(
}
}
+ {
+ struct radeon_bo *bo;
+ bo = !image->mt ? image->bo : image->mt->bo;
+ if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) {
+ radeon_print(RADEON_TEXTURE, RADEON_VERBOSE,
+ "%s Calling teximage for texture that is "
+ "queued for GPU processing.\n",
+ __func__);
+ radeon_firevertices(rmesa);
+ }
+ }
+
/* Upload texture image; note that the spec allows pixels to be NULL */
if (compressed) {
pixels = _mesa_validate_pbo_compressed_teximage(
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