Mesa (7.9): intel: Make renderbuffer tiling choice match texture tiling choice.

[Ian Romanick]

Module: Mesa
Branch: 7.9
Commit: fc09445c879808c153831341d94d4835cd98ae82
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc09445c879808c153831341d94d4835cd98ae82

Author: Eric Anholt <eric at anholt.net>
Date:   Fri Jan  7 18:18:50 2011 -0800

intel: Make renderbuffer tiling choice match texture tiling choice.

There really shouldn't be any difference between the two for us.
Fixes a bug where Z16 renderbuffers would be untiled on gen6, likely
leading to hangs.
(cherry picked from commit 29c4f95cbcad29d52bf3b6c875840b38b8823e4c)
(cherry picked from commit 4e0d6cf7bad7ef15995693d58348fcb7f47120d3)

---

 src/mesa/drivers/dri/intel/intel_fbo.c |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 41d60e6..23c755a 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -177,10 +177,15 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
    DBG("Allocating %d x %d Intel RBO\n", width, height);
 
    tiling = I915_TILING_NONE;
-
-   /* Gen6 requires depth must be tiling */
-   if (intel->gen >= 6 && rb->Format == MESA_FORMAT_S8_Z24)
-       tiling = I915_TILING_Y;
+   if (intel->use_texture_tiling) {
+      GLenum base_format = _mesa_get_format_base_format(rb->Format);
+
+      if (intel->gen >= 4 && (base_format == GL_DEPTH_COMPONENT ||
+			      base_format == GL_DEPTH_STENCIL))
+	 tiling = I915_TILING_Y;
+      else
+	 tiling = I915_TILING_X;
+   }
 
    irb->region = intel_region_alloc(intel->intelScreen, tiling, cpp,
 				    width, height, GL_TRUE);