Mesa (master): i965: Fix VB packet reuse when offset for the new buffer isn 't stride aligned.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 9e872a5865c66ed0a518dd1c6c54e72f3afa71f1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e872a5865c66ed0a518dd1c6c54e72f3afa71f1

Author: Eric Anholt <eric at anholt.net>
Date:   Mon Feb 21 16:24:41 2011 -0800

i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.

Fixes regression in scissor-stencil-clear and 5 other tests.

---

 src/mesa/drivers/dri/i965/brw_draw_upload.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 17af046..b15c05a 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -470,7 +470,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
 	 d = brw->vb.buffers[i].offset - brw->vb.current_buffers[i].offset;
 	 if (delta == 0)
 	    delta = d / brw->vb.current_buffers[i].stride;
-	 else if (delta * brw->vb.current_buffers[i].stride != d)
+	 if (delta * brw->vb.current_buffers[i].stride != d)
 	    break;
       }