Mesa (master): i965: Use 3D clears on gen6+ to avoid inter-ring synchronization.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: a0e5affb22da50aeb30262f5ba0912b059d858ea
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0e5affb22da50aeb30262f5ba0912b059d858ea

Author: Eric Anholt <eric at anholt.net>
Date:   Thu May 19 11:02:14 2011 -0700

i965: Use 3D clears on gen6+ to avoid inter-ring synchronization.

Improves firefox-talos-gfx around 5%.

---

 src/mesa/drivers/dri/intel/intel_clear.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c
index 81c062f..76d33f9 100644
--- a/src/mesa/drivers/dri/intel/intel_clear.c
+++ b/src/mesa/drivers/dri/intel/intel_clear.c
@@ -116,13 +116,13 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
    }
 
    /* HW color buffers (front, back, aux, generic FBO, etc) */
-   if (colorMask == ~0) {
+   if (intel->gen < 6 && colorMask == ~0) {
       /* clear all R,G,B,A */
       blit_mask |= (mask & BUFFER_BITS_COLOR);
    }
    else {
       /* glColorMask in effect */
-      tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
+      tri_mask |= (mask & BUFFER_BITS_COLOR);
    }
 
    /* Make sure we have up to date buffers before we start looking at