Mesa (master): i965: Align index to type size and flush if the type changes
Chris Wilson
ickle at kemper.freedesktop.org
Fri Mar 4 10:00:33 UTC 2011
Module: Mesa
Branch: master
Commit: 1546291e5b8d3ac02f5bee38252f9d479bcf95cc
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1546291e5b8d3ac02f5bee38252f9d479bcf95cc
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Thu Mar 3 15:56:39 2011 +0000
i965: Align index to type size and flush if the type changes
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_context.h | 4 ++--
src/mesa/drivers/dri/i965/brw_draw_upload.c | 21 ++++++++++++++-------
src/mesa/drivers/dri/intel/intel_buffer_objects.c | 6 +++---
src/mesa/drivers/dri/intel/intel_buffer_objects.h | 1 +
src/mesa/drivers/dri/intel/intel_tex_image.c | 3 ++-
5 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 897220b..26a6388 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -517,9 +517,9 @@ struct brw_context
*/
const struct _mesa_index_buffer *ib;
- /* Updates to these fields are signaled by BRW_NEW_INDEX_BUFFER. */
+ /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
drm_intel_bo *bo;
- unsigned int offset;
+ GLuint type;
/* Offset to index buffer index to use in CMD_3D_PRIM so that we can
* avoid re-uploading the IB packet over and over if we're actually
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 351ae07..4478ef9 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -343,7 +343,8 @@ static void brw_prepare_vertices(struct brw_context *brw)
struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
/* Named buffer object: Just reference its contents directly. */
- buffer->bo = intel_bufferobj_source(intel, intel_buffer,
+ buffer->bo = intel_bufferobj_source(intel,
+ intel_buffer, type_size,
&buffer->offset);
drm_intel_bo_reference(buffer->bo);
buffer->offset += (uintptr_t)glarray->Ptr;
@@ -670,7 +671,6 @@ static void brw_prepare_indices(struct brw_context *brw)
intel_upload_data(&brw->intel, index_buffer->ptr, ib_size, ib_type_size,
&bo, &offset);
brw->ib.start_vertex_offset = offset / ib_type_size;
- offset = 0;
} else {
offset = (GLuint) (unsigned long) index_buffer->ptr;
@@ -687,7 +687,6 @@ static void brw_prepare_indices(struct brw_context *brw)
intel_upload_data(&brw->intel, map, ib_size, ib_type_size,
&bo, &offset);
brw->ib.start_vertex_offset = offset / ib_type_size;
- offset = 0;
ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
} else {
@@ -697,22 +696,30 @@ static void brw_prepare_indices(struct brw_context *brw)
*/
brw->ib.start_vertex_offset = offset / ib_type_size;
- bo = intel_bufferobj_source(intel, intel_buffer_object(bufferobj),
+ bo = intel_bufferobj_source(intel,
+ intel_buffer_object(bufferobj),
+ ib_type_size,
&offset);
drm_intel_bo_reference(bo);
+
+ brw->ib.start_vertex_offset += offset / ib_type_size;
}
}
- if (brw->ib.bo != bo || brw->ib.offset != offset) {
+ if (brw->ib.bo != bo) {
drm_intel_bo_unreference(brw->ib.bo);
brw->ib.bo = bo;
- brw->ib.offset = offset;
brw_add_validated_bo(brw, brw->ib.bo);
brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
} else {
drm_intel_bo_unreference(bo);
}
+
+ if (index_buffer->type != brw->ib.type) {
+ brw->ib.type = index_buffer->type;
+ brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER;
+ }
}
const struct brw_tracked_state brw_indices = {
@@ -739,7 +746,7 @@ static void brw_emit_index_buffer(struct brw_context *brw)
1);
OUT_RELOC(brw->ib.bo,
I915_GEM_DOMAIN_VERTEX, 0,
- brw->ib.offset);
+ 0);
OUT_RELOC(brw->ib.bo,
I915_GEM_DOMAIN_VERTEX, 0,
brw->ib.bo->size - 1);
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index 2f750a7..439d6fc 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -723,11 +723,11 @@ void intel_upload_unmap(struct intel_context *intel,
drm_intel_bo *
intel_bufferobj_source(struct intel_context *intel,
struct intel_buffer_object *intel_obj,
- GLuint *offset)
+ GLuint align, GLuint *offset)
{
if (intel_obj->buffer == NULL) {
intel_upload_data(intel,
- intel_obj->sys_buffer, intel_obj->Base.Size, 64,
+ intel_obj->sys_buffer, intel_obj->Base.Size, align,
&intel_obj->buffer, &intel_obj->offset);
intel_obj->source = 1;
}
@@ -782,7 +782,7 @@ intel_bufferobj_copy_subdata(struct gl_context *ctx,
/* Otherwise, we have real BOs, so blit them. */
dst_bo = intel_bufferobj_buffer(intel, intel_dst, INTEL_WRITE_PART);
- src_bo = intel_bufferobj_source(intel, intel_src, &src_offset);
+ src_bo = intel_bufferobj_source(intel, intel_src, 64, &src_offset);
intel_emit_linear_blit(intel,
dst_bo, write_offset,
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.h b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
index 3ec3a52..81ee21f 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.h
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.h
@@ -68,6 +68,7 @@ drm_intel_bo *intel_bufferobj_buffer(struct intel_context *intel,
GLuint flag);
drm_intel_bo *intel_bufferobj_source(struct intel_context *intel,
struct intel_buffer_object *obj,
+ GLuint align,
GLuint *offset);
void intel_upload_data(struct intel_context *intel,
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 1ffc197..906f8a6 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -237,7 +237,8 @@ try_pbo_upload(struct intel_context *intel,
{
GLuint offset;
- drm_intel_bo *src_buffer = intel_bufferobj_source(intel, pbo, &offset);
+ drm_intel_bo *src_buffer =
+ intel_bufferobj_source(intel, pbo, 64, &offset);
if (!intelEmitCopyBlit(intel,
intelImage->mt->cpp,
More information about the mesa-commit
mailing list