Mesa (master): r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().

[Henri Verbeet]

Module: Mesa
Branch: master
Commit: 1a8dc1539b59ab61a6f81a4de32b69978dded7ff
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a8dc1539b59ab61a6f81a4de32b69978dded7ff

Author: Henri Verbeet <hverbeet at gmail.com>
Date:   Mon Mar 14 22:07:44 2011 +0100

r600g: Properly update MULTIWRITE_ENABLE in r600_pipe_shader_ps().

This sort of worked because blend state setup cleared MULTIWRITE_ENABLE again,
but that's not something we want to depend on.

Signed-off-by: Henri Verbeet <hverbeet at gmail.com>

---

 src/gallium/drivers/r600/evergreen_state.c |    1 +
 src/gallium/drivers/r600/r600_state.c      |   14 ++++++--------
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index fedca3b..7743266 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1438,6 +1438,7 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader
 	r600_pipe_state_add_reg(rstate,
 				R_02884C_SQ_PGM_EXPORTS_PS,
 				exports_ps, 0xFFFFFFFF, NULL);
+	/* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
 	/* only set some bits here, the other bits are set in the dsa state */
 	r600_pipe_state_add_reg(rstate,
 				R_02880C_DB_SHADER_CONTROL,
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 2afa374..7378b30 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -152,8 +152,9 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
 		}
 	}
 	blend->cb_target_mask = target_mask;
+	/* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
 	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
-				color_control, 0xFFFFFFFF, NULL);
+				color_control, 0xFFFFFFFD, NULL);
 
 	for (int i = 0; i < 8; i++) {
 		unsigned eqRGB = state->rt[i].rgb_func;
@@ -1297,13 +1298,10 @@ void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shad
 	r600_pipe_state_add_reg(rstate,
 				R_0288CC_SQ_PGM_CF_OFFSET_PS,
 				0x00000000, 0xFFFFFFFF, NULL);
-
-	if (rshader->fs_write_all) {
-		r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
-					S_028808_MULTIWRITE_ENABLE(1),
-					S_028808_MULTIWRITE_ENABLE(1),
-					NULL);
-	}
+	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
+				S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
+				S_028808_MULTIWRITE_ENABLE(1),
+				NULL);
 	/* only set some bits here, the other bits are set in the dsa state */
 	r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
 				db_shader_control,