Mesa (master): i965: Add defines for surface state setup using bitfield shifting.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 7d437b1f7fb64f187125a393eebe1d1c17db9961
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d437b1f7fb64f187125a393eebe1d1c17db9961

Author: Eric Anholt <eric at anholt.net>
Date:   Tue May 31 12:03:52 2011 -0700

i965: Add defines for surface state setup using bitfield shifting.

It turns out that gcc is just awful at generating code for
brw_structs.h style state setup, and using bitshifting on u32s
generates better code while being similarly readable (and more
verifiable compared to the specs, using the INTEL_MASK macro).

---

 src/mesa/drivers/dri/i965/brw_defines.h |   34 ++++++++++++++++++++++++++++++-
 1 files changed, 33 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 5eb7892..84b51c8 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -28,7 +28,10 @@
   * Authors:
   *   Keith Whitwell <keith at tungstengraphics.com>
   */
- 
+
+#define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
+#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)
+#define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
 
 #ifndef BRW_DEFINES_H
 #define BRW_DEFINES_H
@@ -243,8 +246,11 @@
 #define BRW_STENCILOP_DECR               6
 #define BRW_STENCILOP_INVERT             7
 
+/* Surface state DW0 */
+#define BRW_SURFACE_MIPLAYOUT_SHIFT	10
 #define BRW_SURFACE_MIPMAPLAYOUT_BELOW   0
 #define BRW_SURFACE_MIPMAPLAYOUT_RIGHT   1
+#define BRW_SURFACE_CUBEFACE_ENABLES	0x3f
 
 #define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT             0x000 
 #define BRW_SURFACEFORMAT_R32G32B32A32_SINT              0x001 
@@ -403,10 +409,14 @@
 #define BRW_SURFACEFORMAT_R16G16B16_SNORM                0x19D 
 #define BRW_SURFACEFORMAT_R16G16B16_SSCALED              0x19E 
 #define BRW_SURFACEFORMAT_R16G16B16_USCALED              0x19F
+#define BRW_SURFACE_FORMAT_SHIFT	18
+#define BRW_SURFACE_FORMAT_MASK		INTEL_MASK(26, 18)
 
 #define BRW_SURFACERETURNFORMAT_FLOAT32  0
 #define BRW_SURFACERETURNFORMAT_S1       1
 
+#define BRW_SURFACE_TYPE_SHIFT		29
+#define BRW_SURFACE_TYPE_MASK		INTEL_MASK(31, 29)
 #define BRW_SURFACE_1D      0
 #define BRW_SURFACE_2D      1
 #define BRW_SURFACE_3D      2
@@ -414,6 +424,28 @@
 #define BRW_SURFACE_BUFFER  4
 #define BRW_SURFACE_NULL    7
 
+/* Surface state DW2 */
+#define BRW_SURFACE_HEIGHT_SHIFT	19
+#define BRW_SURFACE_HEIGHT_MASK		INTEL_MASK(31, 19)
+#define BRW_SURFACE_WIDTH_SHIFT		6
+#define BRW_SURFACE_WIDTH_MASK		INTEL_MASK(18, 6)
+#define BRW_SURFACE_LOD_SHIFT		2
+#define BRW_SURFACE_LOD_MASK		INTEL_MASK(5, 2)
+
+/* Surface state DW3 */
+#define BRW_SURFACE_DEPTH_SHIFT		21
+#define BRW_SURFACE_DEPTH_MASK		INTEL_MASK(31, 21)
+#define BRW_SURFACE_PITCH_SHIFT		3
+#define BRW_SURFACE_PITCH_MASK		INTEL_MASK(19, 3)
+#define BRW_SURFACE_TILED		(1 << 1)
+#define BRW_SURFACE_TILED_Y		(1 << 0)
+
+/* Surface state DW5 */
+#define BRW_SURFACE_X_OFFSET_SHIFT	25
+#define BRW_SURFACE_X_OFFSET_MASK	INTEL_MASK(31, 25)
+#define BRW_SURFACE_Y_OFFSET_SHIFT	20
+#define BRW_SURFACE_Y_OFFSET_MASK	INTEL_MASK(23, 20)
+
 #define BRW_TEXCOORDMODE_WRAP            0
 #define BRW_TEXCOORDMODE_MIRROR          1
 #define BRW_TEXCOORDMODE_CLAMP           2