Mesa (master): r600g: flush caches regardless of render condition
Marek Olšák
mareko at kemper.freedesktop.org
Thu Nov 10 18:02:49 UTC 2011
Module: Mesa
Branch: master
Commit: 30a570e450da30fa73546c0ff54b4757678a5663
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=30a570e450da30fa73546c0ff54b4757678a5663
Author: Marek Olšák <maraeo at gmail.com>
Date: Thu Nov 10 15:54:17 2011 +0100
r600g: flush caches regardless of render condition
What if somebody enables render condition just before we flush...
---
src/gallium/drivers/r600/r600_hw_context.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index ecb7357..7a84862 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -962,7 +962,7 @@ void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
{
r600_need_cs_space(ctx, 5, FALSE);
- ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
@@ -988,7 +988,7 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
if ((ctx->screen->family == CHIP_RV670) ||
(ctx->screen->family == CHIP_RS780) ||
(ctx->screen->family == CHIP_RS880)) {
- ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */
ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */
ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */
@@ -996,17 +996,17 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
}
}
- ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH;
}
} else {
- ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
ctx->pm4[ctx->pm4_cdwords++] = flush_flags;
ctx->pm4[ctx->pm4_cdwords++] = (bo->buf->size + 255) >> 8;
ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
- ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing);
+ ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0);
ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, bo, RADEON_USAGE_WRITE);
}
bo->cs_buf->last_flush = (bo->cs_buf->last_flush | flush_flags) & flush_mask;
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