Mesa (master): i965: Clarify check for which cache to use on Gen6 data port reads.

Kenneth Graunke kwg at
Tue Oct 18 15:57:12 PDT 2011

Module: Mesa
Branch: master
Commit: bbea5c5a5a7fb327d4ef03f80fe19cfa8d8edccd

Author: Kenneth Graunke <kenneth at>
Date:   Fri Oct  7 21:45:34 2011 -0700

i965: Clarify check for which cache to use on Gen6 data port reads.

Currently, we use the Render Cache for scratch access (read/write data)
and the Sampler Cache for all read only data (pull constants).

Reversing the condition here is clearer: if the caller requested the
Render Cache, use that.  Otherwise, they requested the Data Cache
(which does not exist on Gen6) or Sampler Cache, so use the Sampler

This should not change behavior in any way.

Signed-off-by: Kenneth Graunke <kenneth at>


 src/mesa/drivers/dri/i965/brw_eu_emit.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 7f6ed68..7773cff 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -626,10 +626,10 @@ brw_set_dp_read_message(struct brw_compile *p,
    } else if (intel->gen == 6) {
       uint32_t target_function;
-      if (target_cache == BRW_DATAPORT_READ_TARGET_DATA_CACHE)
-      else
+      if (target_cache == BRW_DATAPORT_READ_TARGET_RENDER_CACHE)
+      else
       insn->bits3.gen6_dp.binding_table_index = binding_table_index;
       insn->bits3.gen6_dp.msg_control = msg_control;

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