Mesa (master): r600g/llvm: Handle copies between vector registers
Tom Stellard
tstellar at kemper.freedesktop.org
Mon Apr 23 14:33:37 UTC 2012
Module: Mesa
Branch: master
Commit: b3863eb9a5a7a844f04acde5f15151c898ff3bac
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3863eb9a5a7a844f04acde5f15151c898ff3bac
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Fri Apr 20 09:07:37 2012 -0400
r600g/llvm: Handle copies between vector registers
---
src/gallium/drivers/radeon/R600GenRegisterInfo.pl | 1 +
src/gallium/drivers/radeon/R600InstrInfo.cpp | 22 +++++++++++++++++++-
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600GenRegisterInfo.pl b/src/gallium/drivers/radeon/R600GenRegisterInfo.pl
index 396a69f..cbded11 100644
--- a/src/gallium/drivers/radeon/R600GenRegisterInfo.pl
+++ b/src/gallium/drivers/radeon/R600GenRegisterInfo.pl
@@ -85,6 +85,7 @@ def R600_Reg128 : RegisterClass<"AMDIL", [v4f32], 128, (add
$t128_string)>
{
let SubRegClasses = [(R600_TReg32 sel_x, sel_y, sel_z, sel_w)];
+ let CopyCost = -1;
}
STRING
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index 80adf8c..0c7ffc4 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -39,8 +39,26 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const
{
- BuildMI(MBB, MI, DL, get(AMDIL::MOV), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
+
+ unsigned subRegMap[4] = {AMDIL::sel_x, AMDIL::sel_y, AMDIL::sel_z, AMDIL::sel_w};
+
+ if (AMDIL::R600_Reg128RegClass.contains(DestReg)
+ && AMDIL::R600_Reg128RegClass.contains(SrcReg)) {
+ for (unsigned i = 0; i < 4; i++) {
+ BuildMI(MBB, MI, DL, get(AMDIL::MOV))
+ .addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
+ .addReg(RI.getSubReg(SrcReg, subRegMap[i]))
+ .addReg(DestReg, RegState::Define | RegState::Implicit);
+ }
+ } else {
+
+ /* We can't copy vec4 registers */
+ assert(!AMDIL::R600_Reg128RegClass.contains(DestReg)
+ && !AMDIL::R600_Reg128RegClass.contains(SrcReg));
+
+ BuildMI(MBB, MI, DL, get(AMDIL::MOV), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ }
}
unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
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