Mesa (8.0): r600g: 128 bit formats require tile_type = 1 on cayman

[Michel Dänzer]

Module: Mesa
Branch: 8.0
Commit: fca1a33c96f2063bbaa4a6898fef1e41a197073d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fca1a33c96f2063bbaa4a6898fef1e41a197073d

Author: Alex Deucher <alexander.deucher at amd.com>
Date:   Fri Feb 10 11:02:03 2012 -0500

r600g: 128 bit formats require tile_type = 1 on cayman

Noticed by taiu on IRC.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

(cherry picked from commit 5e1495b2d9311fa2b320766a1d299053904bd9c3)

Conflicts:

	src/gallium/drivers/r600/evergreen_state.c

---

 src/gallium/drivers/r600/evergreen_state.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 9fd5855..83699e3 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1093,6 +1093,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 		      util_format_get_blockwidth(state->format), 8);
 	array_mode = tmp->array_mode[0];
 	tile_type = tmp->tile_type;
+	/* 128 bit formats require tile type = 1 */
+	if (rctx->chip_class == CAYMAN) {
+		if (util_format_get_blocksize(state->format) >= 16)
+			tile_type = 1;
+	}
 
 	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
 	        height = 1;
@@ -1461,6 +1466,11 @@ static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state
 		tile_type = rtex->tile_type;
 	} else /* workaround for linear buffers */
 		tile_type = 1;
+	/* 128 bit formats require tile type = 1 */
+	if (rctx->chip_class == CAYMAN) {
+		if (util_format_get_blocksize(surf->base.format) >= 16)
+			tile_type = 1;
+	}
 
 	/* FIXME handle enabling of CB beyond BASE8 which has different offset */
 	r600_pipe_state_add_reg(rstate,