Mesa (master): i965: Replace references to stencil region size with buffer size

[Chad Versace]

Module: Mesa
Branch: master
Commit: bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9

Author: Chad Versace <chad.versace at linux.intel.com>
Date:   Wed Dec 21 16:58:38 2011 -0800

i965: Replace references to stencil region size with buffer size

It is unwise to use a stencil region's size to determine its
renderbuffer's size, because at region creation we fudge the width and
height to accomodate interleaved rows. (See the comment for MESA_FORMAT_S8
in intel_miptree_create()). Most users of stencil_region->{width,height}
should be converted to use stencil_rb->{Width,Height}.

We have already done the replacement in several locations. This patch
continues the replacement in {brw,gen7}_emit_depthbuffer(). To make those
functions look consistent, I've also done the equivalent replacement for
the depth buffer.

Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>

---

 src/mesa/drivers/dri/i965/brw_misc_state.c  |    8 ++++----
 src/mesa/drivers/dri/i965/gen7_misc_state.c |    6 ++++--
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1c0c52b..726d8d8 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -343,8 +343,8 @@ static void emit_depthbuffer(struct brw_context *brw)
 	        (1 << 27) | /* tiled surface */
 	        (BRW_SURFACE_2D << 29));
       OUT_BATCH(0);
-      OUT_BATCH(((region->width - 1) << 6) |
-	         (2 * region->height - 1) << 19);
+      OUT_BATCH(((stencil_irb->Base.Width - 1) << 6) |
+	         (stencil_irb->Base.Height - 1) << 19);
       OUT_BATCH(0);
       OUT_BATCH(0);
 
@@ -378,8 +378,8 @@ static void emit_depthbuffer(struct brw_context *brw)
 		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		offset);
       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
-		((region->width - 1) << 6) |
-		((region->height - 1) << 19));
+		((depth_irb->Base.Width - 1) << 6) |
+		((depth_irb->Base.Height - 1) << 19));
       OUT_BATCH(0);
 
       if (intel->is_g4x || intel->gen >= 5)
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 89a4e71..9c93046 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -71,7 +71,8 @@ static void emit_depthbuffer(struct brw_context *brw)
 
 	 /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */
 	 dw1 |= (BRW_SURFACE_2D << 29);
-	 dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18);
+	 dw3 = ((srb->Base.Width - 1) << 4) |
+	       ((srb->Base.Height - 1) << 18);
       }
 
       BEGIN_BATCH(7);
@@ -103,7 +104,8 @@ static void emit_depthbuffer(struct brw_context *brw)
       OUT_RELOC(region->bo,
 	        I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		offset);
-      OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18));
+      OUT_BATCH(((drb->Base.Width - 1) << 4) |
+                ((drb->Base.Height - 1) << 18));
       OUT_BATCH(0);
       OUT_BATCH(tile_x | (tile_y << 16));
       OUT_BATCH(0);