Mesa (master): i965/msaa: Control multisampling behaviour via the visual.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 691c55f3560e5b8b9db9ecd2c089f13b41ec684f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=691c55f3560e5b8b9db9ecd2c089f13b41ec684f

Author: Paul Berry <stereotype441 at gmail.com>
Date:   Mon Jul  9 20:05:41 2012 -0700

i965/msaa: Control multisampling behaviour via the visual.

Previously, we used the number of samples in draw buffer 0 to
determine whether to set up the 3D pipeline for multisampling.  Using
the visual is cleaner, and has the benefit of working properly when
there is no color buffer.

Fixes all piglit tests "EXT_framebuffer_multisample/no-color" on Gen7.
On Gen6, the "depth-computed" variants of these tests still fail; this
will be addresed in a later patch.

Reviewed-by: Chad Versace <chad.versace at linux.intel.com>

---

 src/mesa/drivers/dri/i965/gen6_multisample_state.c |    8 +++-----
 src/mesa/drivers/dri/i965/gen6_sf_state.c          |    4 +---
 src/mesa/drivers/dri/i965/gen6_wm_state.c          |    4 +---
 src/mesa/drivers/dri/i965/gen7_sf_state.c          |    4 +---
 src/mesa/drivers/dri/i965/gen7_wm_state.c          |    4 +---
 5 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index f0648c3..336e7c5 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -83,20 +83,18 @@ static void upload_multisample_state(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &intel->ctx;
-   unsigned num_samples = 0;
    float coverage = 1.0;
    float coverage_invert = false;
 
+   /* _NEW_BUFFERS */
+   unsigned num_samples = ctx->DrawBuffer->Visual.samples;
+
    /* _NEW_MULTISAMPLE */
    if (ctx->Multisample._Enabled && ctx->Multisample.SampleCoverage) {
       coverage = ctx->Multisample.SampleCoverageValue;
       coverage_invert = ctx->Multisample.SampleCoverageInvert;
    }
 
-   /* _NEW_BUFFERS */
-   if (ctx->DrawBuffer->_ColorDrawBuffers[0])
-      num_samples = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples;
-
    /* 3DSTATE_MULTISAMPLE is nonpipelined. */
    intel_emit_post_sync_nonzero_flush(intel);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index aeed369..736e83a 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -122,9 +122,7 @@ upload_sf_state(struct brw_context *brw)
    int i;
    /* _NEW_BUFFER */
    bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
-   bool multisampled_fbo = false;
-   if (ctx->DrawBuffer->_ColorDrawBuffers[0])
-      multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
+   bool multisampled_fbo = ctx->DrawBuffer->Visual.sampleBuffers;
 
    int attr = 0, input_index = 0;
    int urb_entry_read_offset = 1;
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index fa83ece..05f4ab9 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -98,11 +98,9 @@ upload_wm_state(struct brw_context *brw)
    const struct brw_fragment_program *fp =
       brw_fragment_program_const(brw->fragment_program);
    uint32_t dw2, dw4, dw5, dw6;
-   bool multisampled_fbo = false;
 
    /* _NEW_BUFFERS */
-   if (ctx->DrawBuffer->_ColorDrawBuffers[0])
-      multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
+   bool multisampled_fbo = ctx->DrawBuffer->Visual.sampleBuffers;
 
     /* CACHE_NEW_WM_PROG */
    if (brw->wm.prog_data->nr_params == 0) {
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index b1fe654..2d258d2 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -161,9 +161,7 @@ upload_sf_state(struct brw_context *brw)
    float point_size;
    /* _NEW_BUFFERS */
    bool render_to_fbo = _mesa_is_user_fbo(brw->intel.ctx.DrawBuffer);
-   bool multisampled_fbo = false;
-   if (ctx->DrawBuffer->_ColorDrawBuffers[0])
-      multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
+   bool multisampled_fbo = ctx->DrawBuffer->Visual.sampleBuffers;
 
    dw1 = GEN6_SF_STATISTICS_ENABLE |
          GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 8e4417e..e60027a 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -39,12 +39,10 @@ upload_wm_state(struct brw_context *brw)
    const struct brw_fragment_program *fp =
       brw_fragment_program_const(brw->fragment_program);
    bool writes_depth = false;
-   bool multisampled_fbo = false;
    uint32_t dw1, dw2;
 
    /* _NEW_BUFFERS */
-   if (ctx->DrawBuffer->_ColorDrawBuffers[0])
-      multisampled_fbo = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
+   bool multisampled_fbo = ctx->DrawBuffer->Visual.sampleBuffers;
 
    dw1 = dw2 = 0;
    dw1 |= GEN7_WM_STATISTICS_ENABLE;