Mesa (master): radeon/llvm: Remove AMDIL ROUND_NEAREST instruction

[Tom Stellard]

Module: Mesa
Branch: master
Commit: ea00632fe0667766783fb66f9db5198554fee159
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea00632fe0667766783fb66f9db5198554fee159

Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Wed May 23 13:59:32 2012 -0400

radeon/llvm: Remove AMDIL ROUND_NEAREST instruction

---

 src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl |    2 +-
 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp |    3 +++
 src/gallium/drivers/radeon/AMDILInstructions.td   |    2 --
 src/gallium/drivers/radeon/R600Instructions.td    |    5 ++---
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index 654f24f..1ba3afe 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -54,7 +54,7 @@ my $FILE_TYPE = $ARGV[0];
 
 open AMDIL, '<', 'AMDILInstructions.td';
 
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32', 'ROUND_NEAREST_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32');
 
 while (<AMDIL>) {
   if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 1a4c0c4..3ce446f 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -30,6 +30,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
   // Library functions.  These default to Expand, but we have instructions
   // for them.
   setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
+  setOperationAction(ISD::FRINT,  MVT::f32, Legal);
 
 }
 
@@ -79,6 +80,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     case AMDGPUIntrinsic::AMDGPU_umin:
       return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
                                                   Op.getOperand(2));
+    case AMDGPUIntrinsic::AMDIL_round_nearest:
+      return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
     case AMDGPUIntrinsic::AMDIL_round_posinf:
       return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
   }
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index 76a238d..fe451ea 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -215,8 +215,6 @@ def LUSHR        : TwoInOneOut<IL_OP_U64_SHR, (outs GPRI64:$dst),
 let mayLoad=0, mayStore=0 in {
 defm ABS : UnaryIntrinsicFloat<IL_OP_ABS, int_AMDIL_fabs>;
 defm PIREDUCE : UnaryIntrinsicFloat<IL_OP_PI_REDUCE, int_AMDIL_pireduce>;
-defm ROUND_NEAREST : UnaryIntrinsicFloat<IL_OP_ROUND_NEAR,
-          int_AMDIL_round_nearest>;
 defm ROUND_NEGINF : UnaryIntrinsicFloat<IL_OP_ROUND_NEG_INF,
           int_AMDIL_round_neginf>;
 defm ROUND_ZERO : UnaryIntrinsicFloat<IL_OP_ROUND_ZERO,
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index e64d499..92e3cc1 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -373,9 +373,8 @@ def CEIL : R600_1OP <
 
 def RNDNE : R600_1OP <
   0x13, "RNDNE",
-  [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> {
-  let AMDILOp = AMDILInst.ROUND_NEAREST_f32;
-}
+  [(set R600_Reg32:$dst, (frint R600_Reg32:$src))]
+>;
 
 def FLOOR : R600_1OP <
   0x14, "FLOOR",