Mesa (master): radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)
Tom Stellard
tstellar at kemper.freedesktop.org
Thu May 24 19:05:32 UTC 2012
Module: Mesa
Branch: master
Commit: 177b420283547e472632bc650f218ad4b0b541d5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=177b420283547e472632bc650f218ad4b0b541d5
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu May 24 08:55:15 2012 -0400
radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl | 7 -
src/gallium/drivers/radeon/AMDGPUUtil.cpp | 1 -
src/gallium/drivers/radeon/AMDILConversions.td | 589 ---------------------
src/gallium/drivers/radeon/AMDILISelLowering.cpp | 75 ---
src/gallium/drivers/radeon/AMDILInstrPatterns.td | 2 -
src/gallium/drivers/radeon/AMDILInstructions.td | 6 -
src/gallium/drivers/radeon/R600InstrInfo.cpp | 4 -
src/gallium/drivers/radeon/R600Instructions.td | 15 +-
8 files changed, 6 insertions(+), 693 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index ab3415e..7192acc 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -31,10 +31,6 @@
use warnings;
use strict;
-my @I32_MULTICLASSES = qw {
- BinaryOpMCi32Const
-};
-
my @GENERATION_ENUM = qw {
R600_CAYMAN
R600
@@ -52,9 +48,6 @@ my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'U
while (<AMDIL>) {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)</) {
- if (grep {$_ eq $2} @I32_MULTICLASSES) {
- push @INST_ENUMS, "$1\_i32";
- }
} elsif ($_ =~ /def\s+([A-Z_]+)(_[fi]32)/) {
push @INST_ENUMS, "$1$2";
}
diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.cpp b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
index d845574..50e4777 100644
--- a/src/gallium/drivers/radeon/AMDGPUUtil.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
@@ -51,7 +51,6 @@ bool AMDGPU::isTransOp(unsigned opcode)
case AMDIL::MULLIT:
case AMDIL::MUL_LIT_r600:
case AMDIL::MUL_LIT_eg:
- case AMDIL::SHR_i32:
case AMDIL::SIN_f32:
case AMDIL::EXP_IEEE_r600:
case AMDIL::EXP_IEEE_eg:
diff --git a/src/gallium/drivers/radeon/AMDILConversions.td b/src/gallium/drivers/radeon/AMDILConversions.td
deleted file mode 100644
index bf10480..0000000
--- a/src/gallium/drivers/radeon/AMDILConversions.td
+++ /dev/null
@@ -1,589 +0,0 @@
-//==- AMDILConversions.td - Type conversion tablegen patterns -*-tablegen -*-=//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//==-----------------------------------------------------------------------===//
-def actos_i16:Pat < (i16 (anyext GPRI8:$src)),
-(IL_ASSHORT_i32
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))) >;
-
-
-def uctos_i16:Pat < (i16 (zext GPRI8:$src)),
-(IL_ASSHORT_i32
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))) >;
-
-
-def sctos_i16:Pat < (i16 (sext GPRI8:$src)),
-(IL_ASSHORT_i32
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))) >;
-
-
-def actoi_i32:Pat < (i32 (anyext GPRI8:$src)),
-(IL_ASINT_i32
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))) >;
-
-
-def uctoi_i32:Pat < (i32 (zext GPRI8:$src)),
-(IL_ASINT_i32
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))) >;
-
-
-def sctoi_i32:Pat < (i32 (sext GPRI8:$src)),
-(IL_ASINT_i32
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))) >;
-
-
-def actol_i64:Pat < (i64 (anyext GPRI8:$src)),
-(LCREATE
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 0)) >;
-
-
-def uctol_i64:Pat < (i64 (zext GPRI8:$src)),
-(LCREATE
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 0)) >;
-
-
-def sctol_i64:Pat < (i64 (sext GPRI8:$src)),
-(LCREATE
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24)),
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 31))) >;
-
-
-def astoi_i32:Pat < (i32 (anyext GPRI16:$src)),
-(IL_ASINT_i32
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16))) >;
-
-
-def ustoi_i32:Pat < (i32 (zext GPRI16:$src)),
-(IL_ASINT_i32
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16))) >;
-
-
-def sstoi_i32:Pat < (i32 (sext GPRI16:$src)),
-(IL_ASINT_i32
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16))) >;
-
-
-def astol_i64:Pat < (i64 (anyext GPRI16:$src)),
-(LCREATE
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 0)) >;
-
-
-def ustol_i64:Pat < (i64 (zext GPRI16:$src)),
-(LCREATE
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 0)) >;
-
-
-def sstol_i64:Pat < (i64 (sext GPRI16:$src)),
-(LCREATE
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16)),
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 31))) >;
-
-
-def aitol_i64:Pat < (i64 (anyext GPRI32:$src)),
-(LCREATE
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i32 GPRI32:$src),
- (LOADCONST_i32 0)),
- (LOADCONST_i32 0)),
- (LOADCONST_i32 0)) >;
-
-
-def uitol_i64:Pat < (i64 (zext GPRI32:$src)),
-(LCREATE
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i32 GPRI32:$src),
- (LOADCONST_i32 0)),
- (LOADCONST_i32 0)),
- (LOADCONST_i32 0)) >;
-
-
-def sitol_i64:Pat < (i64 (sext GPRI32:$src)),
-(LCREATE
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i32 GPRI32:$src),
- (LOADCONST_i32 0)),
- (LOADCONST_i32 0)),
- (SHR_i32
- (SHL_i32
-(IL_ASINT_i32 GPRI32:$src),
- (LOADCONST_i32 0)),
- (LOADCONST_i32 31))) >;
-
-
-
-def uctof_f32:Pat < (f32 (uint_to_fp GPRI8:$src)),
-(f32
- (UTOF
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24)))) >;
-
-
-def uctod_f64:Pat < (f64 (uint_to_fp GPRI8:$src)),
-(f64 (FTOD
- (UTOF
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i8 GPRI8:$src),
- (LOADCONST_i32 24)),
- (LOADCONST_i32 24))))) >;
-
-def ustof_f32:Pat < (f32 (uint_to_fp GPRI16:$src)),
-(f32
- (UTOF
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16)))) >;
-
-def ustod_f64:Pat < (f64 (uint_to_fp GPRI16:$src)),
-(f64 (FTOD
- (UTOF
- (USHR_i32
- (SHL_i32
-(IL_ASINT_i16 GPRI16:$src),
- (LOADCONST_i32 16)),
- (LOADCONST_i32 16))))) >;
-
-
-def actos_v2i16:Pat < (v2i16 (anyext GPRV2I8:$src)),
-(IL_ASV2SHORT_v2i32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))) >;
-
-
-def uctos_v2i16:Pat < (v2i16 (zext GPRV2I8:$src)),
-(IL_ASV2SHORT_v2i32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))) >;
-
-
-def sctos_v2i16:Pat < (v2i16 (sext GPRV2I8:$src)),
-(IL_ASV2SHORT_v2i32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))) >;
-
-
-def actoi_v2i32:Pat < (v2i32 (anyext GPRV2I8:$src)),
-(IL_ASV2INT_v2i32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))) >;
-
-
-def uctoi_v2i32:Pat < (v2i32 (zext GPRV2I8:$src)),
-(IL_ASV2INT_v2i32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))) >;
-
-
-def sctoi_v2i32:Pat < (v2i32 (sext GPRV2I8:$src)),
-(IL_ASV2INT_v2i32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))) >;
-
-
-def actol_v2i64:Pat < (v2i64 (anyext GPRV2I8:$src)),
-(LCREATE_v2i64
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 0))) >;
-
-
-def uctol_v2i64:Pat < (v2i64 (zext GPRV2I8:$src)),
-(LCREATE_v2i64
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 0))) >;
-
-
-def sctol_v2i64:Pat < (v2i64 (sext GPRV2I8:$src)),
-(LCREATE_v2i64
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 31)))) >;
-
-
-def astoi_v2i32:Pat < (v2i32 (anyext GPRV2I16:$src)),
-(IL_ASV2INT_v2i32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16)))) >;
-
-
-def ustoi_v2i32:Pat < (v2i32 (zext GPRV2I16:$src)),
-(IL_ASV2INT_v2i32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16)))) >;
-
-
-def sstoi_v2i32:Pat < (v2i32 (sext GPRV2I16:$src)),
-(IL_ASV2INT_v2i32
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16)))) >;
-
-
-def astol_v2i64:Pat < (v2i64 (anyext GPRV2I16:$src)),
-(LCREATE_v2i64
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 0))) >;
-
-
-def ustol_v2i64:Pat < (v2i64 (zext GPRV2I16:$src)),
-(LCREATE_v2i64
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 0))) >;
-
-
-def sstol_v2i64:Pat < (v2i64 (sext GPRV2I16:$src)),
-(LCREATE_v2i64
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 31)))) >;
-
-
-def aitol_v2i64:Pat < (v2i64 (anyext GPRV2I32:$src)),
-(LCREATE_v2i64
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i32 GPRV2I32:$src),
- (VCREATE_v2i32 (LOADCONST_i32 0))),
- (VCREATE_v2i32 (LOADCONST_i32 0))),
- (VCREATE_v2i32 (LOADCONST_i32 0))) >;
-
-
-def uitol_v2i64:Pat < (v2i64 (zext GPRV2I32:$src)),
-(LCREATE_v2i64
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i32 GPRV2I32:$src),
- (VCREATE_v2i32 (LOADCONST_i32 0))),
- (VCREATE_v2i32 (LOADCONST_i32 0))),
- (VCREATE_v2i32 (LOADCONST_i32 0))) >;
-
-
-def sitol_v2i64:Pat < (v2i64 (sext GPRV2I32:$src)),
-(LCREATE_v2i64
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i32 GPRV2I32:$src),
- (VCREATE_v2i32 (LOADCONST_i32 0))),
- (VCREATE_v2i32 (LOADCONST_i32 0))),
- (SHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i32 GPRV2I32:$src),
- (VCREATE_v2i32 (LOADCONST_i32 0))),
- (VCREATE_v2i32 (LOADCONST_i32 31)))) >;
-
-
-
-def uctof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I8:$src)),
-(v2f32
- (UTOF_v2f32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24))))) >;
-
-
-def uctod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I8:$src)),
-(v2f64
- (VINSERT_v2f64
- (VCREATE_v2f64
- (FTOD
- (VEXTRACT_v2f32
- (UTOF_v2f32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))),
- 1)
- )),
- (FTOD
- (VEXTRACT_v2f32
- (UTOF_v2f32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i8 GPRV2I8:$src),
- (VCREATE_v2i32 (LOADCONST_i32 24))),
- (VCREATE_v2i32 (LOADCONST_i32 24)))),
- 2)
- ), 1, 256)
- ) >;
-
-
-def ustof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I16:$src)),
-(v2f32
- (UTOF_v2f32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16))))) >;
-
-
-def ustod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I16:$src)),
-(v2f64
- (VINSERT_v2f64
- (VCREATE_v2f64
- (FTOD
- (VEXTRACT_v2f32
- (UTOF_v2f32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16)))),
- 1)
- )),
- (FTOD
- (VEXTRACT_v2f32
- (UTOF_v2f32
- (USHRVEC_v2i32
- (SHLVEC_v2i32
-(IL_ASV2INT_v2i16 GPRV2I16:$src),
- (VCREATE_v2i32 (LOADCONST_i32 16))),
- (VCREATE_v2i32 (LOADCONST_i32 16)))),
- 2)
- ), 1, 256)
- ) >;
-
-
-def actos_v4i16:Pat < (v4i16 (anyext GPRV4I8:$src)),
-(IL_ASV4SHORT_v4i32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24)))) >;
-
-
-def uctos_v4i16:Pat < (v4i16 (zext GPRV4I8:$src)),
-(IL_ASV4SHORT_v4i32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24)))) >;
-
-
-def sctos_v4i16:Pat < (v4i16 (sext GPRV4I8:$src)),
-(IL_ASV4SHORT_v4i32
- (SHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24)))) >;
-
-
-def actoi_v4i32:Pat < (v4i32 (anyext GPRV4I8:$src)),
-(IL_ASV4INT_v4i32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24)))) >;
-
-
-def uctoi_v4i32:Pat < (v4i32 (zext GPRV4I8:$src)),
-(IL_ASV4INT_v4i32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24)))) >;
-
-
-def sctoi_v4i32:Pat < (v4i32 (sext GPRV4I8:$src)),
-(IL_ASV4INT_v4i32
- (SHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24)))) >;
-
-
-def astoi_v4i32:Pat < (v4i32 (anyext GPRV4I16:$src)),
-(IL_ASV4INT_v4i32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i16 GPRV4I16:$src),
- (VCREATE_v4i32 (LOADCONST_i32 16))),
- (VCREATE_v4i32 (LOADCONST_i32 16)))) >;
-
-
-def ustoi_v4i32:Pat < (v4i32 (zext GPRV4I16:$src)),
-(IL_ASV4INT_v4i32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i16 GPRV4I16:$src),
- (VCREATE_v4i32 (LOADCONST_i32 16))),
- (VCREATE_v4i32 (LOADCONST_i32 16)))) >;
-
-
-def sstoi_v4i32:Pat < (v4i32 (sext GPRV4I16:$src)),
-(IL_ASV4INT_v4i32
- (SHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i16 GPRV4I16:$src),
- (VCREATE_v4i32 (LOADCONST_i32 16))),
- (VCREATE_v4i32 (LOADCONST_i32 16)))) >;
-
-
-
-def uctof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I8:$src)),
-(v4f32
- (UTOF_v4f32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i8 GPRV4I8:$src),
- (VCREATE_v4i32 (LOADCONST_i32 24))),
- (VCREATE_v4i32 (LOADCONST_i32 24))))) >;
-
-
-def ustof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I16:$src)),
-(v4f32
- (UTOF_v4f32
- (USHRVEC_v4i32
- (SHLVEC_v4i32
-(IL_ASV4INT_v4i16 GPRV4I16:$src),
- (VCREATE_v4i32 (LOADCONST_i32 16))),
- (VCREATE_v4i32 (LOADCONST_i32 16))))) >;
-
diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
index ca213d1..dae63fa 100644
--- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp
@@ -492,81 +492,6 @@ AMDILTargetLowering::LowerMemArgument(
//===----------------------------------------------------------------------===//
// Instruction generation functions
//===----------------------------------------------------------------------===//
-uint32_t
-AMDILTargetLowering::addExtensionInstructions(
- uint32_t reg, bool signedShift,
- unsigned int simpleVT) const
-{
- int shiftSize = 0;
- uint32_t LShift, RShift;
- switch(simpleVT)
- {
- default:
- return reg;
- case AMDIL::GPRI8RegClassID:
- shiftSize = 24;
- LShift = AMDIL::SHL_i8;
- if (signedShift) {
- RShift = AMDIL::SHR_i8;
- } else {
- RShift = AMDIL::USHR_i8;
- }
- break;
- case AMDIL::GPRV2I8RegClassID:
- shiftSize = 24;
- LShift = AMDIL::SHL_v2i8;
- if (signedShift) {
- RShift = AMDIL::SHR_v2i8;
- } else {
- RShift = AMDIL::USHR_v2i8;
- }
- break;
- case AMDIL::GPRV4I8RegClassID:
- shiftSize = 24;
- LShift = AMDIL::SHL_v4i8;
- if (signedShift) {
- RShift = AMDIL::SHR_v4i8;
- } else {
- RShift = AMDIL::USHR_v4i8;
- }
- break;
- case AMDIL::GPRI16RegClassID:
- shiftSize = 16;
- LShift = AMDIL::SHL_i16;
- if (signedShift) {
- RShift = AMDIL::SHR_i16;
- } else {
- RShift = AMDIL::USHR_i16;
- }
- break;
- case AMDIL::GPRV2I16RegClassID:
- shiftSize = 16;
- LShift = AMDIL::SHL_v2i16;
- if (signedShift) {
- RShift = AMDIL::SHR_v2i16;
- } else {
- RShift = AMDIL::USHR_v2i16;
- }
- break;
- case AMDIL::GPRV4I16RegClassID:
- shiftSize = 16;
- LShift = AMDIL::SHL_v4i16;
- if (signedShift) {
- RShift = AMDIL::SHR_v4i16;
- } else {
- RShift = AMDIL::USHR_v4i16;
- }
- break;
- };
- uint32_t LoadReg = genVReg(simpleVT);
- uint32_t tmp1 = genVReg(simpleVT);
- uint32_t tmp2 = genVReg(simpleVT);
- generateMachineInst(AMDIL::LOADCONST_i32, LoadReg).addImm(shiftSize);
- generateMachineInst(LShift, tmp1, reg, LoadReg);
- generateMachineInst(RShift, tmp2, tmp1, LoadReg);
- return tmp2;
-}
-
MachineOperand
AMDILTargetLowering::convertToReg(MachineOperand op) const
{
diff --git a/src/gallium/drivers/radeon/AMDILInstrPatterns.td b/src/gallium/drivers/radeon/AMDILInstrPatterns.td
index cd01ea4..a1e7e1f 100644
--- a/src/gallium/drivers/radeon/AMDILInstrPatterns.td
+++ b/src/gallium/drivers/radeon/AMDILInstrPatterns.td
@@ -33,5 +33,3 @@ def : Pat<(IL_call texternalsym:$dst),
(CALL texternalsym:$dst)>;
def : Pat<(IL_call tconstpool:$dst),
(CALL tconstpool:$dst)>;
-
-include "AMDILConversions.td"
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td b/src/gallium/drivers/radeon/AMDILInstructions.td
index cdc2808..cb31bdd 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -53,10 +53,6 @@ def INTTOANY_i16: OneInOneOut<IL_OP_MOV, (outs GPRI16:$dst), (ins GPRI32:$src0),
defm NEGATE : UnaryOpMCi32<IL_OP_I_NEGATE, IL_inegate>;
defm SMUL : BinaryOpMCi32<IL_OP_I_MUL, mul>;
defm SMULHI : BinaryOpMCi32<IL_OP_I_MUL_HIGH, mulhs>;
-defm SHL : BinaryOpMCi32Const<IL_OP_I_SHL, shl>;
-defm SHR : BinaryOpMCi32Const<IL_OP_I_SHR, sra>;
-defm SHLVEC : BinaryOpMCi32<IL_OP_I_SHL, shl>;
-defm SHRVEC : BinaryOpMCi32<IL_OP_I_SHR, sra>;
// get rid of the addri via the tablegen instead of custom lowered instruction
defm EADD : BinaryOpMCi32<IL_OP_I_ADD, adde>;
def INTTOANY_i32: OneInOneOut<IL_OP_MOV, (outs GPRI32:$dst), (ins GPRI32:$src0),
@@ -118,8 +114,6 @@ def FTOV4U8_i32 : OneInOneOut<IL_OP_F2U4, (outs GPRI32:$dst),
//===---------------------------------------------------------------------===//
defm UMUL : BinaryOpMCi32<IL_OP_U_MUL, IL_umul>;
defm UMULHI : BinaryOpMCi32<IL_OP_U_MUL_HIGH, mulhu>;
-defm USHR : BinaryOpMCi32Const<IL_OP_U_SHR, srl>;
-defm USHRVEC : BinaryOpMCi32<IL_OP_U_SHR, srl>;
defm UDIV : BinaryOpMCi32<IL_OP_U_DIV, udiv>;
defm NATIVE_UDIV : BinaryIntrinsicInt<IL_OP_U_DIV, int_AMDIL_udiv>;
let mayLoad=0, mayStore=0 in {
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index 01d3d0d..42a2257 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -74,14 +74,10 @@ unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
case AMDIL::MOVE_f32:
case AMDIL::MOVE_i32:
return AMDIL::MOV;
- case AMDIL::SHR_i32:
- return getASHRop();
case AMDIL::UGE:
return AMDIL::SETGE_UINT;
case AMDIL::UGT:
return AMDIL::SETGT_UINT;
- case AMDIL::USHR_i32:
- return getLSHRop();
}
}
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 6873fc6..a242776 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -648,21 +648,18 @@ class LOG_IEEE_Common <bits<32> inst> : R600_1OP <
class LSHL_Common <bits<32> inst> : R600_2OP <
inst, "LSHL $dst, $src0, $src1",
- [] >{
- let AMDILOp = AMDILInst.SHL_i32;
-}
+ [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
class LSHR_Common <bits<32> inst> : R600_2OP <
inst, "LSHR $dst, $src0, $src1",
- [] >{
- let AMDILOp = AMDILInst.USHR_i32;
-}
+ [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
class ASHR_Common <bits<32> inst> : R600_2OP <
inst, "ASHR $dst, $src0, $src1",
- [] >{
- let AMDILOp = AMDILInst.SHR_i32;
-}
+ [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
class MULHI_INT_Common <bits<32> inst> : R600_2OP <
inst, "MULHI_INT $dst, $src0, $src1",
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