Mesa (master): i965/blorp: Use 16 pixel dispatch on Gen7.

Paul Berry stereotype441 at kemper.freedesktop.org
Fri May 25 15:45:33 UTC 2012


Module: Mesa
Branch: master
Commit: f2cdfa4c8522b6b0f5d1b0a6c42ed39e0d47c876
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2cdfa4c8522b6b0f5d1b0a6c42ed39e0d47c876

Author: Paul Berry <stereotype441 at gmail.com>
Date:   Wed May  9 17:14:56 2012 -0700

i965/blorp: Use 16 pixel dispatch on Gen7.

Gen7 hardware requires us to enable at least one WM dispatch mode,
even if there is no program being dispatched to.  When this code was
only used for HiZ operations (which don't use a WM program), we used
32-pixel dispatch, because it didn't matter.  But blit programs are
compiled for 16-pixel dispatch.  So just enable 16-wide dispatch
unconditionally.

Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

v2: Enable 16-wide dispatch unconditionally rather than add the
unnecessary complication of using 32-wide dispatch when there is no WM
program.

---

 src/mesa/drivers/dri/i965/gen7_blorp.cpp |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index b41717d..04548bf 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -472,7 +472,15 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
 
    dw2 = dw4 = dw5 = 0;
    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
-   dw4 |= GEN7_PS_32_DISPATCH_ENABLE;
+
+   /* If there's a WM program, we need to do 16-pixel dispatch since that's
+    * what the program is compiled for.  If there isn't, then it shouldn't
+    * matter because no program is actually being run.  However, the hardware
+    * gets angry if we don't enable at least one dispatch mode, so just enable
+    * 16-pixel dispatch unconditionally.
+    */
+   dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
+
    if (intel->is_haswell)
       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
    if (params->use_wm_prog) {




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