Mesa (master): i965/msaa: Add defines for Gen7.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 0e11b2c5afca456e19b1c29889dde449a4072ede
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e11b2c5afca456e19b1c29889dde449a4072ede

Author: Paul Berry <stereotype441 at gmail.com>
Date:   Tue May  8 15:29:43 2012 -0700

i965/msaa: Add defines for Gen7.

Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_defines.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 467a418..ff6cc6e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -439,6 +439,9 @@
 #define BRW_SURFACE_BUFFER  4
 #define BRW_SURFACE_NULL    7
 
+#define GEN7_SURFACE_ARYSPC_FULL	0
+#define GEN7_SURFACE_ARYSPC_LOD0	1
+
 /* Surface state DW2 */
 #define BRW_SURFACE_HEIGHT_SHIFT	19
 #define BRW_SURFACE_HEIGHT_MASK		INTEL_MASK(31, 19)
@@ -463,6 +466,8 @@
 #define GEN7_SURFACE_MULTISAMPLECOUNT_1 0
 #define GEN7_SURFACE_MULTISAMPLECOUNT_4 2
 #define GEN7_SURFACE_MULTISAMPLECOUNT_8 3
+#define GEN7_SURFACE_MSFMT_MSS			0
+#define GEN7_SURFACE_MSFMT_DEPTH_STENCIL	1
 
 /* Surface state DW5 */
 #define BRW_SURFACE_X_OFFSET_SHIFT		25