Mesa (master): gallivm: clear Altivec NJ bit

[Jose Fonseca]

Module: Mesa
Branch: master
Commit: 29ba79b2c929ea23b45fa065fe7c9f8fd400210c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=29ba79b2c929ea23b45fa065fe7c9f8fd400210c

Author: Adhemerval Zanella <azanella at linux.vnet.ibm.com>
Date:   Thu Nov 22 11:55:35 2012 -0600

gallivm: clear Altivec NJ bit

This patch enforces the clear of NJ bit in VSCR Altivec register so
denormal numbers are handles as expected by IEEE standards.

Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>

---

 src/gallium/auxiliary/gallivm/lp_bld_init.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index 0065bb4..050eba7 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -468,6 +468,25 @@ lp_build_init(void)
       util_cpu_caps.has_avx = 0;
    }
 
+#ifdef PIPE_ARCH_PPC_64
+   /* Set the NJ bit in VSCR to 0 so denormalized values are handled as
+    * specified by IEEE standard (PowerISA 2.06 - Section 6.3). This garantees
+    * that some rounding and half-float to float handling does not round
+    * incorrectly to 0.
+    */
+   if (util_cpu_caps.has_altivec) {
+      unsigned short mask[] = { 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
+                                0xFFFF, 0xFFFF, 0xFFFE, 0xFFFF };
+      __asm (
+        "mfvscr %%v1\n"
+        "vand   %0,%%v1,%0\n"
+        "mtvscr %0"
+        :
+        : "r" (*mask)
+      );
+   }
+#endif
+
    gallivm_initialized = TRUE;
 
 #if 0