Mesa (master): radeonsi: Better indexing of parameters in the pixel shader.

[Michel Dänzer]

Module: Mesa
Branch: master
Commit: c3db19efba8ccdf8df94ab357cf675ba8728f81c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3db19efba8ccdf8df94ab357cf675ba8728f81c

Author: Michel Dänzer <michel.daenzer at amd.com>
Date:   Thu Sep 27 20:01:33 2012 +0200

radeonsi: Better indexing of parameters in the pixel shader.

We were previously using the TGSI input index, which can exceed the number of
parameters passed from the vertex shader via the parameter cache. Now we use
a separate index which only counts those parameters.

Prevents piglit regressions with the following fix.

Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

---

 src/gallium/drivers/radeonsi/radeonsi_shader.c |   10 ++++++----
 src/gallium/drivers/radeonsi/radeonsi_shader.h |    1 +
 src/gallium/drivers/radeonsi/si_state_draw.c   |    9 +++++----
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 75cb7e1..a48234a 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -236,6 +236,7 @@ static void declare_input_fs(
 {
 	const char * intr_name;
 	unsigned chan;
+	struct si_shader *shader = &si_shader_ctx->shader->shader;
 	struct lp_build_context * base =
 				&si_shader_ctx->radeon_bld.soa.bld_base.base;
 	struct gallivm_state * gallivm = base->gallivm;
@@ -249,10 +250,7 @@ static void declare_input_fs(
 	 *
 	 */
 	LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, SI_PS_NUM_USER_SGPR);
-
-
-	/* XXX: Is this the input_index? */
-	LLVMValueRef attr_number = lp_build_const_int32(gallivm, input_index);
+	LLVMValueRef attr_number;
 
 	if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
 		for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
@@ -268,6 +266,10 @@ static void declare_input_fs(
 		return;
 	}
 
+	shader->input[input_index].param_offset = shader->ninterp++;
+	attr_number = lp_build_const_int32(gallivm,
+					   shader->input[input_index].param_offset);
+
 	/* XXX: Handle all possible interpolation modes */
 	switch (decl->Interp.Interpolate) {
 	case TGSI_INTERPOLATE_COLOR:
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 688db57..4583e62 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -71,6 +71,7 @@ struct si_shader {
 	unsigned		noutput;
 	struct si_shader_io	output[32];
 
+	unsigned		ninterp;
 	bool			uses_kill;
 	bool			fs_write_all;
 	unsigned		nr_cbufs;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index a431afe..e62ef71 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -101,7 +101,6 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
 	struct si_pm4_state *pm4;
 	unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
 	unsigned num_sgprs, num_user_sgprs;
-	int ninterp = 0;
 	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
 	unsigned fragcoord_interp_mode = 0;
 	unsigned spi_baryc_cntl, spi_ps_input_ena;
@@ -131,7 +130,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
 			}
 			continue;
 		}
-		ninterp++;
+
 		/* XXX: Flat shading hangs the GPU */
 		if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
 		    (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
@@ -172,7 +171,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *s
 		exports_ps = 2;
 	}
 
-	spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
+	spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp);
 
 	spi_baryc_cntl = 0;
 	if (have_perspective)
@@ -365,7 +364,9 @@ static void si_update_spi_map(struct r600_context *rctx)
 			tmp |= S_028644_OFFSET(0x20);
 		}
 
-		si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp);
+		si_pm4_set_reg(pm4,
+			       R_028644_SPI_PS_INPUT_CNTL_0 + ps->input[i].param_offset * 4,
+			       tmp);
 	}
 
 	si_pm4_set_state(rctx, spi, pm4);