Mesa (master): radeon/llvm: Fix lowering of SI_V_CNDLT

[Tom Stellard]

Module: Mesa
Branch: master
Commit: 446d19c12a576e36c3da34ada01b708fcbc196c5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=446d19c12a576e36c3da34ada01b708fcbc196c5

Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Tue Sep  4 11:20:01 2012 -0400

radeon/llvm: Fix lowering of SI_V_CNDLT

SREG_LIT_0 is a scalar register, so it can only be used in the
first argument of vector instructoins.

---

 src/gallium/drivers/radeon/SIISelLowering.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp
index a64e2a3..2c81673 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -235,10 +235,10 @@ void SITargetLowering::LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB,
 void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
     MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
 {
-  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32),
+  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_GT_F32_e32),
           AMDGPU::VCC)
-          .addOperand(MI->getOperand(1))
-          .addReg(AMDGPU::SREG_LIT_0);
+          .addReg(AMDGPU::SREG_LIT_0)
+          .addOperand(MI->getOperand(1));
 
   BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
           .addOperand(MI->getOperand(0))