Mesa (master): radeon/llvm: Add SHADER_TYPE instruction

[Tom Stellard]

Module: Mesa
Branch: master
Commit: dfd3d61abfc8b2dc7300636ed5308f0a83953017
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfd3d61abfc8b2dc7300636ed5308f0a83953017

Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Fri Sep  7 09:11:59 2012 -0400

radeon/llvm: Add SHADER_TYPE instruction

This allows the program to specify the type of shader being compiled
(e.g. PXEL, VERTEX, etc.)

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>

---

 src/gallium/drivers/radeon/AMDGPU.h                |    9 +++++++++
 src/gallium/drivers/radeon/AMDGPUInstructions.td   |    7 +++++++
 src/gallium/drivers/radeon/AMDGPUIntrinsics.td     |    2 ++
 src/gallium/drivers/radeon/R600ISelLowering.cpp    |    1 +
 src/gallium/drivers/radeon/SIAssignInterpRegs.cpp  |    4 ++++
 src/gallium/drivers/radeon/SIISelLowering.cpp      |    6 ++++++
 .../drivers/radeon/SIMachineFunctionInfo.cpp       |    3 ++-
 src/gallium/drivers/radeon/SIMachineFunctionInfo.h |    1 +
 8 files changed, 32 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h
index ab6871c..fe36545 100644
--- a/src/gallium/drivers/radeon/AMDGPU.h
+++ b/src/gallium/drivers/radeon/AMDGPU.h
@@ -33,4 +33,13 @@ FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
 
 } // End namespace llvm
 
+namespace ShaderType {
+  enum Type {
+    PIXEL = 0,
+    VERTEX = 1,
+    GEOMETRY = 2,
+    COMPUTE = 3
+  };
+}
+
 #endif // AMDGPU_H
diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index c8a7db6..6f47445 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -114,6 +114,13 @@ class FNEG <RegisterClass rc> : AMDGPUShaderInst <
   [(set rc:$dst, (fneg rc:$src0))]
 >;
 
+def SHADER_TYPE : AMDGPUShaderInst <
+  (outs),
+  (ins i32imm:$type),
+  "SHADER_TYPE $type",
+  [(int_AMDGPU_shader_type imm:$type)]
+>;
+
 } // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1
 
 /* Generic helper patterns for intrinsics */
diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
index 89cc7e1..958e0bd 100644
--- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
@@ -54,6 +54,8 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
   def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
   def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
   def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
+
+  def int_AMDGPU_shader_type : Intrinsic<[], [llvm_i32_ty], []>;
 }
 
 let TargetPrefix = "TGSI", isTarget = 1 in {
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 5642ee8..5a82920 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -61,6 +61,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
 
   switch (MI->getOpcode()) {
   default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
+  case AMDGPU::SHADER_TYPE: break;
   case AMDGPU::CLAMP_R600:
     {
       MachineInstr *NewMI =
diff --git a/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp b/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp
index 3ee03ae..447eff6 100644
--- a/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp
+++ b/src/gallium/drivers/radeon/SIAssignInterpRegs.cpp
@@ -87,6 +87,10 @@ bool SIAssignInterpRegsPass::runOnMachineFunction(MachineFunction &MF)
   };
 
   SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
+  // This pass is only needed for pixel shaders.
+  if (MFI->ShaderType != ShaderType::PIXEL) {
+    return false;
+  }
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   /* First pass, mark the interpolation values that are used. */
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp
index ebe9514..42c2e7f 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -16,6 +16,7 @@
 #include "AMDIL.h"
 #include "AMDILIntrinsicInfo.h"
 #include "SIInstrInfo.h"
+#include "SIMachineFunctionInfo.h"
 #include "SIRegisterInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -122,6 +123,11 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
                  .addImm(1); // NEG
     MI->eraseFromParent();
     break;
+  case AMDGPU::SHADER_TYPE:
+    BB->getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType =
+                                        MI->getOperand(0).getImm();
+    MI->eraseFromParent();
+    break;
 
   case AMDGPU::SI_INTERP:
     LowerSI_INTERP(MI, *BB, I, MRI);
diff --git a/src/gallium/drivers/radeon/SIMachineFunctionInfo.cpp b/src/gallium/drivers/radeon/SIMachineFunctionInfo.cpp
index 40ba76f..f1a8c1f 100644
--- a/src/gallium/drivers/radeon/SIMachineFunctionInfo.cpp
+++ b/src/gallium/drivers/radeon/SIMachineFunctionInfo.cpp
@@ -14,5 +14,6 @@ using namespace llvm;
 
 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
   : MachineFunctionInfo(),
-    spi_ps_input_addr(0)
+    spi_ps_input_addr(0),
+    ShaderType(0)
   { }
diff --git a/src/gallium/drivers/radeon/SIMachineFunctionInfo.h b/src/gallium/drivers/radeon/SIMachineFunctionInfo.h
index 46a021f..b60822e 100644
--- a/src/gallium/drivers/radeon/SIMachineFunctionInfo.h
+++ b/src/gallium/drivers/radeon/SIMachineFunctionInfo.h
@@ -28,6 +28,7 @@ class SIMachineFunctionInfo : public MachineFunctionInfo {
   public:
     SIMachineFunctionInfo(const MachineFunction &MF);
     unsigned spi_ps_input_addr;
+    unsigned ShaderType;
 
 };