Mesa (master): r600g: reduce quant mode on evergreen+

[Alex Deucher]

Module: Mesa
Branch: master
Commit: b33d7eaa5e77b5367584fe183c46f8c3d9a06760
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b33d7eaa5e77b5367584fe183c46f8c3d9a06760

Author: Alex Deucher <alexander.deucher at amd.com>
Date:   Thu Sep 13 17:25:42 2012 -0400

r600g: reduce quant mode on evergreen+

Seems to have an affect on the allowable range of
values.  Set evergreen+ to 1/256 to match 6xx/7xx.

fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=54877

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

---

 src/gallium/drivers/r600/evergreen_state.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 56df174..8235c71 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -921,7 +921,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
 	} else {
 		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
-					S_028C08_QUANT_MODE(V_028C08_X_1_4096TH));
+					S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 	}
 	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,