Mesa (master): radeon/llvm: Replace AMDGPU pow intrinsic with the llvm version

[Tom Stellard]

Module: Mesa
Branch: master
Commit: 87decd6e66d145f4af87c871c0f5086b5b17e002
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=87decd6e66d145f4af87c871c0f5086b5b17e002

Author: Tom Stellard <thomas.stellard at amd.com>
Date:   Thu Sep 13 15:04:15 2012 +0000

radeon/llvm: Replace AMDGPU pow intrinsic with the llvm version

---

 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp  |    1 +
 src/gallium/drivers/radeon/AMDGPUInstrInfo.td      |    2 +
 src/gallium/drivers/radeon/AMDGPUInstructions.td   |    2 +-
 .../drivers/radeon/radeon_setup_tgsi_llvm.c        |   28 +++++++++++++++----
 4 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 3f9c820..d6304a2 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -34,6 +34,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
   // for them.
   setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
   setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
+  setOperationAction(ISD::FPOW,   MVT::f32, Legal);
   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
 
   setOperationAction(ISD::UDIV, MVT::i32, Expand);
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.td b/src/gallium/drivers/radeon/AMDGPUInstrInfo.td
index 4452719..23ca35a 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.td
@@ -67,3 +67,5 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
 // out = (2^32 / a) + e
 // e is rounding error
 def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
+
+def fpow : SDNode<"ISD::FPOW", SDTFPBinOp>;
diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index 3e850eb..0194873 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -128,7 +128,7 @@ def SHADER_TYPE : AMDGPUShaderInst <
 
 class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
                   RegisterClass rc> : Pat <
-  (int_AMDGPU_pow rc:$src0, rc:$src1),
+  (fpow rc:$src0, rc:$src1),
   (exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
 >;
 
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 04469e2..3c29122 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -980,17 +980,33 @@ build_intrinsic(LLVMBuilderRef builder,
    return LLVMBuildCall(builder, function, args, num_args, "");
 }
 
-void
-build_tgsi_intrinsic_nomem(
+static void build_tgsi_intrinsic(
  const struct lp_build_tgsi_action * action,
  struct lp_build_tgsi_context * bld_base,
- struct lp_build_emit_data * emit_data)
+ struct lp_build_emit_data * emit_data,
+ LLVMAttribute attr)
 {
    struct lp_build_context * base = &bld_base->base;
    emit_data->output[emit_data->chan] = build_intrinsic(
                base->gallivm->builder, action->intr_name,
                emit_data->dst_type, emit_data->args,
-               emit_data->arg_count, LLVMReadNoneAttribute);
+               emit_data->arg_count, attr);
+}
+void
+build_tgsi_intrinsic_nomem(
+ const struct lp_build_tgsi_action * action,
+ struct lp_build_tgsi_context * bld_base,
+ struct lp_build_emit_data * emit_data)
+{
+	build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute);
+}
+
+static void build_tgsi_intrinsic_readonly(
+ const struct lp_build_tgsi_action * action,
+ struct lp_build_tgsi_context * bld_base,
+ struct lp_build_emit_data * emit_data)
+{
+	build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute);
 }
 
 void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
@@ -1147,8 +1163,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
 	bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
 	bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem;
 	bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul";
-	bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem;
-	bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.AMDGPU.pow";
+	bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly;
+	bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
 	bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem;
 	bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp";
 	bld_base->op_actions[TGSI_OPCODE_SSG].emit = build_tgsi_intrinsic_nomem;