Mesa (master): gallium: clarify shift behavior with shift count >= 32

[Roland Scheidegger]

Module: Mesa
Branch: master
Commit: 606132b4def69f7c5fa0fa436259e2fd163b0768
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=606132b4def69f7c5fa0fa436259e2fd163b0768

Author: Roland Scheidegger <sroland at vmware.com>
Date:   Tue Jul 30 17:08:01 2013 +0200

gallium: clarify shift behavior with shift count >= 32

Previously, nothing was said what happens with shift counts exceeding
bit width of the values to shift. In theory 3 behaviors are possible:
1) undefined (classic c definition)
2) just shift out all bits (so result is zero, or -1 potentially for ashr)
3) mask the shift count to bit width - 1
API's either require 3) or are ok with 1). In particular, GLSL (as well as a
couple uninteresting legacy GL extensions) is happy with undefined, whereas
both OpenCL and d3d10 require 3). Consequently, most hw also implements 3).
So, for simplicity we just specify that 3) is required rather than saying
undefined and then needing state trackers to work around it.
Also while here specify shift count as a vector, not scalar. As far as I
can tell this was a doc bug, neither state trackers nor drivers used scalar
shift count.

Reviewed-by: Jose Fonseca <jfonseca at vmware.com>

---

 src/gallium/docs/source/tgsi.rst |   30 ++++++++++++++++++------------
 1 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 0557ce0..8506b7e 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1254,41 +1254,47 @@ Support for these opcodes indicated by PIPE_SHADER_CAP_INTEGERS (all of them?)
 
 .. opcode:: SHL - Shift Left
 
+   The shift count is masked with 0x1f before the shift is applied.
+
 .. math::
 
-  dst.x = src0.x << src1.x
+  dst.x = src0.x << (0x1f & src1.x)
 
-  dst.y = src0.y << src1.x
+  dst.y = src0.y << (0x1f & src1.y)
 
-  dst.z = src0.z << src1.x
+  dst.z = src0.z << (0x1f & src1.z)
 
-  dst.w = src0.w << src1.x
+  dst.w = src0.w << (0x1f & src1.w)
 
 
 .. opcode:: ISHR - Arithmetic Shift Right (of Signed Integer)
 
+   The shift count is masked with 0x1f before the shift is applied.
+
 .. math::
 
-  dst.x = src0.x >> src1.x
+  dst.x = src0.x >> (0x1f & src1.x)
 
-  dst.y = src0.y >> src1.x
+  dst.y = src0.y >> (0x1f & src1.y)
 
-  dst.z = src0.z >> src1.x
+  dst.z = src0.z >> (0x1f & src1.z)
 
-  dst.w = src0.w >> src1.x
+  dst.w = src0.w >> (0x1f & src1.w)
 
 
 .. opcode:: USHR - Logical Shift Right
 
+   The shift count is masked with 0x1f before the shift is applied.
+
 .. math::
 
-  dst.x = src0.x >> (unsigned) src1.x
+  dst.x = src0.x >> (unsigned) (0x1f & src1.x)
 
-  dst.y = src0.y >> (unsigned) src1.x
+  dst.y = src0.y >> (unsigned) (0x1f & src1.y)
 
-  dst.z = src0.z >> (unsigned) src1.x
+  dst.z = src0.z >> (unsigned) (0x1f & src1.z)
 
-  dst.w = src0.w >> (unsigned) src1.x
+  dst.w = src0.w >> (unsigned) (0x1f & src1.w)
 
 
 .. opcode:: UCMP - Integer Conditional Move