Mesa (master): i965: Set vertical alignment unit to 4 on Broadwell.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 1110ba4c088e41548090d52d669157c3e9f6f9fa
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1110ba4c088e41548090d52d669157c3e9f6f9fa

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Sat Dec 15 01:14:03 2012 -0800

i965: Set vertical alignment unit to 4 on Broadwell.

Broadwell doesn't support a surface vertical alignment of 2.  It only
supports VALIGN_4, VALIGN_8, or VALIGN_16.  I chose 4 since it's the
least wasteful.

v2: Replace my comment with a better one from Eric.  Move Broadwell
    checks earlier so it's more obvious that "return 2" won't be hit.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/brw_tex_layout.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 2c81eed..16af19f 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -117,6 +117,12 @@ intel_vertical_texture_alignment_unit(struct brw_context *brw,
    if (format == MESA_FORMAT_S8)
       return brw->gen >= 7 ? 8 : 4;
 
+   /* Broadwell only supports VALIGN of 4, 8, and 16.  The BSpec says 4
+    * should always be used, except for stencil buffers, which should be 8.
+    */
+   if (brw->gen >= 8)
+      return 4;
+
    if (multisampled)
       return 4;